// Author: Thomas Hadig (Group EB SLAC Stanford CA USA)
// Last update: $Date: 2004/10/04 19:51:58 $
// Copyright: Thomas Hadig, hadig@slac.stanford.edu

#ifndef __CRTSLACADCBOARD_CXX
#define __CRTSLACADCBOARD_CXX

////////////////////////////////////////////////////////////////////////////////
//
// Cosmic Ray Telescope Data Aquisition Software
//
// class for SLAC ADC board. 
//
////////////////////////////////////////////////////////////////////////////////

#include <gendriver/slacadc.hh>
#include <gendriver/vmemmcrate.hh>

namespace CRT 
 { 
  //{{{}}}
  //{{{  constructor
   CrtSLACAdcBoard::CrtSLACAdcBoard()
   {
    // default constructor
   }
  //}}}
  //{{{  constructor CrtSLACAdcBoard(const Char_t *inName, Int_t inIdent, CrtCrate *inCrate)
   CrtSLACAdcBoard::CrtSLACAdcBoard(const Char_t *inName, Int_t inIdent, CrtCrate *inCrate)
    : CrtTdcAdcBoard(inName, inIdent*256, inCrate)
   {
    // constructor
    // inIdent : address of board
    // inCrate : corresponding controler
   }
  //}}}
  //{{{  destructor
   CrtSLACAdcBoard::~CrtSLACAdcBoard()
   {
    // destructor
   }
  //}}}

  //{{{  WaitForData
   Int_t CrtSLACAdcBoard::WaitForData(Int_t inTimeout) const
   {
    // waits until data has arrived in this module
    // inTimeout defines the maximum number of seconds that is waited for 
    // until the function returns. A inTimeout of 0 will cause infinite
    // waiting.
    // return value is 1 if that is available, 0 if the timeout occured
    inTimeout *= 1000;  // seconds * 10^6 / 1 usec wait intervals
    while (HasData()==0)
     {
      if (inTimeout!=0)
       {
        inTimeout--;
        if (inTimeout==0) return 0;
       }
      //usleep(1); // wait 1 micro seconds
     }
    return 1;
   }
  //}}}
  //{{{  Initialize
   Int_t CrtSLACAdcBoard::Initialize() const
   {
    return 1;
   }
  //}}}
  //{{{  Prepare
   Int_t CrtSLACAdcBoard::Prepare() const
   {
    return 1;
   }
  //}}}
  //{{{  Start
   Int_t CrtSLACAdcBoard::Start() const
   {
    return (((CrtVMEMMCrate *)fInCrate))->Send(fIdent*2, 0xA1*2, 0x00);
   }
  //}}}
  //{{{  Stop
   Int_t CrtSLACAdcBoard::Stop() const
   {
    return (((CrtVMEMMCrate *)fInCrate))->Send(fIdent*2, 0xA2*2, 0x00);
   }
  //}}}
  //{{{  HasData
   Int_t CrtSLACAdcBoard::HasData() const
   {
    Int_t val;
    (((CrtVMEMMCrate *)fInCrate))->Read(fIdent*2, 0xA1*2, &val);
    if (val==0xffff) return 0;
    return 1;
   }
  //}}}

  //{{{  Send
   Int_t CrtSLACAdcBoard::Send(Int_t inCommand) const
   {
    // sends command to board
    // available commands:
    // none ...
    return -1;
   }
  //}}}
  //{{{  Enable
   Int_t CrtSLACAdcBoard::Enable(Int_t, Int_t) const
   {
    // enables board features
    // Available features:
    // none ...
    return -1;
   }
  //}}}
  //{{{  Disable
   Int_t CrtSLACAdcBoard::Disable(Int_t, Int_t) const
   {
    // enables board features
    // Available features:
    // none ...
    return -1;
   }
  //}}}
  
  //{{{  Query
   Int_t CrtSLACAdcBoard::Query(Int_t inChannel, Int_t *outValue) const
   {
    // query channels
    // available channels:
    // 0-31: individual input channels event data
    //   (use Select to choose between: Pedestal, Lower or Upper Threshold data)
    // 32: status register
    // 33: ram pointer

    if ((inChannel>=0)&&(inChannel<=31))
      return (((CrtVMEMMCrate *)fInCrate))->Read(fIdent*2, (0x80+inChannel)*2, outValue);
    else if (inChannel==32)
      return (((CrtVMEMMCrate *)fInCrate))->Read(fIdent*2, 0xA1*2, outValue);
    else if (inChannel==33)
      return (((CrtVMEMMCrate *)fInCrate))->Read(fIdent*2, 0xA0*2, outValue);
    return -1;
   }
  //}}}
  //{{{  Assign
   Int_t CrtSLACAdcBoard::Assign(Int_t inChannel, Int_t inValue) const
   {
    // assign channels
    // available channels:
    // 0-31: individual input channels event data
    //   (use Select to choose between: Pedestal, Lower or Upper Threshold data)
    // 32: n/a
    // 33: ram pointer

    if ((inChannel>=0)&&(inChannel<=31))
      return (((CrtVMEMMCrate *)fInCrate))->Send(fIdent*2, (0x80+inChannel)*2, inValue);
    else if (inChannel==33)
      return (((CrtVMEMMCrate *)fInCrate))->Send(fIdent*2, 0xA0*2, inValue);
    return -1;
   }
  //}}}
  //{{{  Test
   Int_t CrtSLACAdcBoard::Test(Int_t inChannel, Int_t) const
   {
    // test channels
    // available channels:
    // 0: status

    if (inChannel==1)
     {
      Int_t val;
      Query(32, &val);
      return val;
     }
    return -1;
   }
  //}}}

  //{{{  ReadModuleAndClear
   Int_t CrtSLACAdcBoard::ReadModuleAndClear(Int_t *outChannels) const
   {
    // reads all channels and clears the data afterwards.
  
    Int_t chanmap[32] = 
     //{{{  
     {
      // Format: real MCP channel //index=ADC channel
      0, //1
      1, //2
      15, //3
      14, //4
      23, //5
      22, //6
      31, //7
      30, //8
      2, //9
      3, //10
      12, //11
      13, //12
      20, //13
      21, //14
      28, //15
      29, //16
      4, //17
      5, //18
      10, //19
      11, //20
      18, //21
      19, //22
      26, //23
      27, //24
      6, //25
      7, //26
      8, //27
      9, //28
      16, //29
      17, //30
      24, //31
      25 //32;
     };
     //}}}
  
    // set RamPointer to last value read
    Int_t rp;
    ((CrtVMEMMCrate *)fInCrate)->Read(fIdent*2, 0xA0, &rp);
    rp = rp -1;
    if (rp <0) rp += 0x10000;
    ((CrtVMEMMCrate *)fInCrate)->Send(fIdent*2, 0xA0, rp);
  
    // read all channels
    Int_t chan = 0,val;
    while (chan<32)
     { 
      if ((((CrtVMEMMCrate *)fInCrate))->Read(fIdent*2, (0x80+chan)*2, &val)== 0)
        return -1;
      outChannels[chanmap[chan]]= val & 0xfff;
      chan++;
     }
    return 32;
   }
  //}}}
  //{{{  GetNumberOfChannels
   Int_t CrtSLACAdcBoard::GetNumberOfChannels() const
   {
    return 32;
   }
  //}}}
 }

ClassImp(CRT::CrtSLACAdcBoard) //generic description of a TDC or ADC board

#endif