include: DigFpga.yaml

#MMIO range, will be attached to FPGA
mmio: &mmio
  name: mmio
  size: 0x100000000 # 4GB of address space
  MMIODev:

    - <<: *DigFpga
      offset: 0x00000000

stream: &stream
    name: Stream0
    SRP:
      ProtocolVersion: SRP_UDP_NONE
    udp:
      port: 8194
      numRxThreads: 2
    RSSI: yes
    depack:
      useDepack: yes
    TDestMux:
      TDEST: 0x80

NetIODev:
  name: fpga
  ipAddr: 10.0.2.104
  MMIODev:
    - <<: *mmio
      SRP:
        ProtocolVersion: SRP_UDP_V3
      udp:
        port: 8193
      RSSI: yes
      depack:
        useDepack: yes
      TDestMux:
        TDEST: 0
  StreamDev:
    - <<: *stream
      name: Stream0
      TDestMux:
        TDEST: 0x80
    - <<: *stream
      name: Stream1
      TDestMux:
        TDEST: 0x81
    - <<: *stream
      name: Stream2
      TDestMux:
        TDEST: 0x82
    - <<: *stream
      name: Stream3
      TDestMux:
        TDEST: 0x83