{
    "ltx_root": {
        "version": 4,
        "minor": 0,
        "ltx_data": [
            {
                "name": "EDA_PROBESET",
                "active": true,
                "debug_cores": [
                    {
                        "type": "XSDB_V3",
                        "name": "dbg_hub",
                        "spec": "labtools_xsdbm_v3",
                        "clk_input_freq_hz": "50000000"
                    },
                    {
                        "type": "XSDBS_V2",
                        "name": "U_Core/U_Core/U_DdrMem/MigCore_Inst",
                        "spec": "labtools_xsdbslavelib_v2",
                        "ipName": "DDR3_SDRAM",
                        "core_location": {
                            "user_chain": 1,
                            "slave_index": 0,
                            "bscan_switch_index": 0
                        }
                    }
                ]
            }
        ]
    }
}