##############################################################################
## This file is part of 'SLAC Firmware Standard Library'.
## It is subject to the license terms in the LICENSE.txt file found in the 
## top-level directory of this distribution and at: 
##    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 
## No part of 'SLAC Firmware Standard Library', including this file, 
## may be copied, modified, propagated, or distributed except according to 
## the terms contained in the LICENSE.txt file.
##############################################################################
#schemaversion 3.0.0
#once

EvrV1Reg: &EvrV1Reg
  class: MMIODev
  configPrio: 1
  description: LCLS-I EVR Registers
  size: 0x8000
  children:
    #########################################################  
    Status:
      at:
        offset: 0x00 # address(14 downto 2) = 0
      class: IntField
      name: Status
      mode: RO
      description: Status Register
    #########################################################  
    Control:
      at:
        offset: 0x04 # address(14 downto 2) = 1
      class: IntField
      name: Control
      mode: RW
      description: Control Register
    #########################################################  
    IrqFlag:
      at:
        offset: 0x08 # address(14 downto 2) = 2
      class: IntField
      name: IrqFlag
      mode: RW
      description: Interrupt Flag Register
    #########################################################  
    IrqEnable:
      at:
        offset: 0x0C # address(14 downto 2) = 3
      class: IntField
      name: IrqEnable
      mode: RW
      description: Interrupt Enable Register
    #########################################################  
    PulseIrqMap:
      at:
        offset: 0x010 # address(14 downto 2) = 4
      class: IntField
      name: PulseIrqMap
      mode: RW
      description: Mapping register for pulse interrupt
    #########################################################  
    PcieIntEna:
      at:
        offset: 0x014 # address(14 downto 2) = 5
      class: IntField
      name: PcieIntEna
      mode: RW
      description: PCIe interrupt Enable and state status
##############################################################  
## Controlled by ISR (not generic register interface)
##############################################################  
#    DataBufCtrl:
#      at:
#        offset: 0x020 # address(14 downto 2) = 8
#      class: IntField
#      name: DataBufCtrl
#      mode: RW
#      description: Data Buffer Control and Status Register
############################################################## 
    FWVersion:
      at:
        offset: 0x02C # address(14 downto 2) = 11
      class: IntField
      name: FWVersion
      mode: RO
      description: Firmware Version Register
    #########################################################  
    FWVersionUnmasked:
      at:
        offset: 0x030 # address(14 downto 2) = 12
      class: IntField
      name: FWVersionUnmasked
      mode: RO
      description: Firmware Version without 0x1F mask and byte swapped
    #########################################################  
    UsecDivider:
      at:
        offset: 0x04C # address(14 downto 2) = 19
      class: IntField
      name: UsecDivider
      mode: RW
      description: Divider to get from Event Clock to 1 MHz
    #########################################################  
    SecSR:
      at:
        offset: 0x05C # address(14 downto 2) = 23
      class: IntField
      name: SecSR
      mode: RO
      description: Seconds Shift Register
    #########################################################  
    SecCounter:
      at:
        offset: 0x060 # address(14 downto 2) = 24
      class: IntField
      name: SecCounter
      mode: RO
      description: Timestamp Seconds Counter
    #########################################################  
    EventCounter:
      at:
        offset: 0x064 # address(14 downto 2) = 25
      class: IntField
      name: EventCounter
      mode: RO
      description: Timestamp Event Counter
    #########################################################  
    SecLatch:
      at:
        offset: 0x068 # address(14 downto 2) = 26
      class: IntField
      name: SecLatch
      mode: RO
      description: Timestamp Seconds Counter Latch
    #########################################################  
    EvCntLatch:
      at:
        offset: 0x06C # address(14 downto 2) = 27
      class: IntField
      name: EvCntLatch
      mode: RO
      description: Timestamp Event Counter Latch
##############################################################  
## Controlled by ISR (not generic register interface)
##############################################################  
#    EvFIFOSec:
#      at:
#        offset: 0x070 # address(14 downto 2) = 28
#      class: IntField
#      name: EvFIFOSec
#      mode: RW
#      description: Event FIFO Seconds Register
##############################################################  
## Controlled by ISR (not generic register interface)
##############################################################  
#    EvFIFOEvCnt:
#      at:
#        offset: 0x074 # address(14 downto 2) = 29
#      class: IntField
#      name: EvFIFOEvCnt
#      mode: RW
#      description: Event FIFO Event Counter Register
##############################################################  
## Controlled by ISR (not generic register interface)
##############################################################  
#    EvFIFOCode:
#      at:
#        offset: 0x078 # address(14 downto 2) = 30
#      class: IntField
#      name: EvFIFOCode
#      sizeBits: 16
#      mode: RW
#      description: Event FIFO Event Code Register
##############################################################  
    IntEventEn:
      at:
        offset: 0x0A0 # address(14 downto 2) = 40
      class: IntField
      name: IntEventEn
      mode: RW
      description: Internal Event Enable
    #########################################################  
    IntEventCount:
      at:
        offset: 0x0A4 # address(14 downto 2) = 41
      class: IntField
      name: IntEventCount
      sizeBits: 1
      mode: RW
      description: Internal Event Count
    #########################################################  
    IntEventCode:
      at:
        offset: 0x0A8 # address(14 downto 2) = 42
      class: IntField
      name: IntEventCode
      sizeBits: 8
      mode: RW
      description: Internal Event Code
    #########################################################  
    ExtEventEn:
      at:
        offset: 0x0AC # address(14 downto 2) = 43
      class: IntField
      name: ExtEventEn
      sizeBits: 1
      mode: RW
      description: External Event Enable
    #########################################################  
    ExtEventCode:
      at:
        offset: 0x0B0 # address(14 downto 2) = 44
      class: IntField
      name: ExtEventCode
      sizeBits: 8
      mode: RW
      description: External Event Code
    #########################################################  
    Pulse00:
      at:
        offset: 0x200 # address(14 downto 2) = [131:128]
        nelms: 4
      class: IntField
      name: Pulse00
      mode: RW
      description: Pulse 0 Registers
    #########################################################  
    Pulse01:
      at:
        offset: 0x210 # address(14 downto 2) = [135:132]
        nelms: 4
      class: IntField
      name: Pulse01
      mode: RW
      description: Pulse 1 Registers
    #########################################################  
    Pulse02:
      at:
        offset: 0x220 # address(14 downto 2) = [139:136]
        nelms: 4
      class: IntField
      name: Pulse02
      mode: RW
      description: Pulse 2 Registers
    #########################################################  
    Pulse03:
      at:
        offset: 0x230 # address(14 downto 2) = [143:140]
        nelms: 4
      class: IntField
      name: Pulse03
      mode: RW
      description: Pulse 3 Registers
    #########################################################  
    Pulse04:
      at:
        offset: 0x240 # address(14 downto 2) = [147:144]
        nelms: 4
      class: IntField
      name: Pulse04
      mode: RW
      description: Pulse 4 Registers
    #########################################################  
    Pulse05:
      at:
        offset: 0x250 # address(14 downto 2) = [151:148]
        nelms: 4
      class: IntField
      name: Pulse05
      mode: RW
      description: Pulse 5 Registers
    #########################################################  
    Pulse06:
      at:
        offset: 0x260 # address(14 downto 2) = [155:152]
        nelms: 4
      class: IntField
      name: Pulse06
      mode: RW
      description: Pulse 6 Registers
    #########################################################  
    Pulse07:
      at:
        offset: 0x270 # address(14 downto 2) = [159:156]
        nelms: 4
      class: IntField
      name: Pulse07
      mode: RW
      description: Pulse 7 Registers
    #########################################################  
    Pulse08:
      at:
        offset: 0x280 # address(14 downto 2) = [163:160]
        nelms: 4
      class: IntField
      name: Pulse08
      mode: RW
      description: Pulse 8 Registers
    #########################################################  
    Pulse09:
      at:
        offset: 0x290 # address(14 downto 2) = [167:164]
        nelms: 4
      class: IntField
      name: Pulse09
      mode: RW
      description: Pulse 9 Registers
    #########################################################  
    Pulse10:
      at:
        offset: 0x2A0 # address(14 downto 2) = [171:168]
        nelms: 4
      class: IntField
      name: Pulse10
      mode: RW
      description: Pulse 10 Registers
    #########################################################  
    Pulse11:
      at:
        offset: 0x2B0 # address(14 downto 2) = [175:172]
        nelms: 4
      class: IntField
      name: Pulse11
      mode: RW
      description: Pulse 11 Registers
    #########################################################  
    OutputMap:
      at:
        offset: 0x440 # address(14 downto 2) = [277:272]
        nelms: 12
      class: IntField
      name: OutputMap
      sizeBits: 16
      mode: RW
      description: Front Panel Output Map Registers [11:0]
##############################################################  
## Controlled by ISR (not generic register interface)
##############################################################  
#    DataBuf:
#      at:
#        offset: 0x800 # address(14 downto 2) = [1023:512]
#        nelms: 512
#      class: IntField
#      name: DataBuf
#      mode: RO
#      description: Data Buffer Receive Memory [511:0]
##############################################################  
    MapRam1:
      at:
        offset: 0x4000 # address(14 downto 2) = [5119:4096]
        nelms: 1024
      class: IntField
      name: MapRam1
      mode: RO
      description: Event Mapping RAM 1 [1023:0]
    #########################################################  
    MapRam2:
      at:
        offset: 0x6000 # address(14 downto 2) = [6143:5120]
        nelms: 1024
      class: IntField
      name: MapRam2
      mode: RO
      description: Event Mapping RAM 2 [1023:0]
    #########################################################  
