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RAD750_dump_private.h File Reference

RAD750 dump library private definitions. More...

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Defines

#define PPCI_VENDOR_ID   0x11d0
#define PPCI_DEVICE_ID   0x0010
#define PPCI_CFG_STATUS2   0x0050
#define PPCI_CFG_STATUS2_MASK   0x0054
#define PPCI_CFG_BAR1_ADJUST   0x0058
#define PPCI_CFG_CONFIG   0x005c
#define PPCI_CFG_ARB_PRI   0x0060
#define PPCI_CFG_ERR_CHECK   0x0062
#define PPCI_CFG_ERR_INJECT   0x0064
#define PPCI_CFG_REVISION_ID   0x0066
#define PPCI_CFG_O2P_IO_0   0x0080
#define PPCI_CFG_O2P_IO_1   0x0082
#define PPCI_CFG_O2P_IO_2   0x0084
#define PPCI_CFG_O2P_IO_3   0x0086
#define PPCI_CFG_O2P_IO_4   0x0088
#define PPCI_CFG_O2P_IO_5   0x008a
#define PPCI_CFG_O2P_IO_6   0x008c
#define PPCI_CFG_O2P_IO_7   0x008e
#define PPCI_CFG_O2P_MEM_0   0x0090
#define PPCI_CFG_O2P_MEM_1   0x0092
#define PPCI_CFG_O2P_MEM_2   0x0094
#define PPCI_CFG_O2P_MEM_3   0x0096
#define PPCI_CFG_O2P_MEM_4   0x0098
#define PPCI_CFG_O2P_MEM_5   0x009a
#define PPCI_CFG_O2P_MEM_6   0x009c
#define PPCI_CFG_O2P_MEM_7   0x009e
#define PPCI_CFG_USER_B   0x00a8
#define PPCI_CFG_USER_C   0x00ac
#define PPCI_CFG_USER_A   0x00c0
#define PPCI_CFG_BUS_ERR_STATUS   0x00c6
#define PPCI_CFG_BUS_ERR_ADDR   0x00c8
#define USERC_NO_SNOOP_ENABLE   0x08000000
#define USERC_FF0_LOCAL   0x04000000
#define USERC_SNOOP_WAIT   0x000c0000
#define USERC_DBWO_ENABLE   0x00008000
#define USERC_ADDR_WAIT   0x0000000c
#define PPCI_ERR_CHK_PROTOCOL   0x0400
#define PPCI_ERR_CHK_RDY_PAR   0x0200
#define PPCI_ERR_CHK_DATA_CONTROL   0x0030
#define PPCI_ERR_CHK_DATA_TIMEOUT   0x0008
#define PPCI_ERR_CHK_ARB_CONTROL   0x0006
#define PPCI_ERR_CHK_ARB_TIMEOUT   0x0001
#define PPCI_VEC_PCI_CRIT_ERR   0x80000000
#define PPCI_VEC_60X_CRIT_ERR   0x40000000
#define PPCI_VEC_JTAG_MAST_CRIT_ERR   0x20000000
#define PPCI_VEC_JTAG_MS_MAST_CRIT_ERR   0x10000000
#define PPCI_VEC_JTAG_MS_SLV_CRIT_ERR   0x08000000
#define PPCI_VEC_MEM_CRIT_ERR   0x04000000
#define PPCI_VEC_OCB_CRIT_ERR   0x02000000
#define PPCI_VEC_UART_CRIT_ERR   0x01000000
#define PPCI_VEC_EMC_CRIT_ERR   0x00800000
#define PPCI_VEC_MISC_CRIT_ERR   0x00400000
#define PPCI_VEC_CAT_CRIT_ERR   0x00200000
#define PPCI_VEC_WDT_EXPIRE   0x00008000
#define PPCI_VEC_CHECKSTOP   0x00004000
#define PPCI_VEC_TIMER_1   0x00002000
#define PPCI_VEC_TIMER_2   0x00001000
#define PPCI_VEC_TIMER_3   0x00000800
#define PPCI_VEC_CPU_INT   0x00000400
#define MEM_ERR_CRITICAL   0x13
#define MEM_ERR_INIT_COMPLETE   0x02
#define MEM_ERR_SCRUB_COMPLETE   0x01
#define MEM_ERR_REFRESH_COMPLETE   0x00
#define CPU_DISC_CRIT_ERR_DISABLE   0x00000008
#define CPU_DISC_CRIT_ERR_INJECT   0x00000004
#define CPU_DISC_CHECK_ENABLE   0x00000002
#define CPU_DISC_HRESET   0x00000001

Detailed Description

RAD750 dump library private definitions.

Author:
D.L. Wood

Define Documentation

#define CPU_DISC_CHECK_ENABLE   0x00000002
 

The PPCI CPU discretes register checkstop enable bit mask.

#define CPU_DISC_CRIT_ERR_DISABLE   0x00000008
 

The PPCI CPU discretes register critical error disable bit mask.

#define CPU_DISC_CRIT_ERR_INJECT   0x00000004
 

The PPCI CPU discretes register critical error injection bit mask.

#define CPU_DISC_HRESET   0x00000001
 

The PPCI CPU discretes register hardware reset bit mask.

#define MEM_ERR_CRITICAL   0x13
 

The bit position in the memory status register for critical error.

#define MEM_ERR_INIT_COMPLETE   0x02
 

The bit position in the memory status register for memory initialization complete.

#define MEM_ERR_REFRESH_COMPLETE   0x00
 

The bit position in the memory status register for memory refresh cycle complete.

#define MEM_ERR_SCRUB_COMPLETE   0x01
 

The bit position in the memory status register for memory scrub cycle complete.

#define PPCI_CFG_ARB_PRI   0x0060
 

The offset to the PPCI configuration arbitration priority register.

#define PPCI_CFG_BAR1_ADJUST   0x0058
 

The offset to the PPCI configuration BAR1 size adjust register.

#define PPCI_CFG_BUS_ERR_ADDR   0x00c8
 

The offset to the PPCI bus error address register.

#define PPCI_CFG_BUS_ERR_STATUS   0x00c6
 

The offset to the PPCI bus error status register.

#define PPCI_CFG_CONFIG   0x005c
 

The offset to the PPCI configuration config register.

#define PPCI_CFG_ERR_CHECK   0x0062
 

The offset to the PPCI configuration error check register.

#define PPCI_CFG_ERR_INJECT   0x0064
 

The offset to the PPCI configuration error injection register.

#define PPCI_CFG_O2P_IO_0   0x0080
 

The offset to the PPCI I/O paging register 0.

#define PPCI_CFG_O2P_IO_1   0x0082
 

The offset to the PPCI I/O paging register 1.

#define PPCI_CFG_O2P_IO_2   0x0084
 

The offset to the PPCI I/O paging register 2.

#define PPCI_CFG_O2P_IO_3   0x0086
 

The offset to the PPCI I/O paging register 3.

#define PPCI_CFG_O2P_IO_4   0x0088
 

The offset to the PPCI I/O paging register 4.

#define PPCI_CFG_O2P_IO_5   0x008a
 

The offset to the PPCI I/O paging register 5.

#define PPCI_CFG_O2P_IO_6   0x008c
 

The offset to the PPCI I/O paging register 6.

#define PPCI_CFG_O2P_IO_7   0x008e
 

The offset to the PPCI I/O paging register 7.

#define PPCI_CFG_O2P_MEM_0   0x0090
 

The offset to the PPCI memory paging register 0.

#define PPCI_CFG_O2P_MEM_1   0x0092
 

The offset to the PPCI memory paging register 1.

#define PPCI_CFG_O2P_MEM_2   0x0094
 

The offset to the PPCI memory paging register 2.

#define PPCI_CFG_O2P_MEM_3   0x0096
 

The offset to the PPCI memory paging register 3.

#define PPCI_CFG_O2P_MEM_4   0x0098
 

The offset to the PPCI memory paging register 4.

#define PPCI_CFG_O2P_MEM_5   0x009a
 

The offset to the PPCI memory paging register 5.

#define PPCI_CFG_O2P_MEM_6   0x009c
 

The offset to the PPCI memory paging register 6.

#define PPCI_CFG_O2P_MEM_7   0x009e
 

The offset to the PPCI memory paging register 7.

#define PPCI_CFG_REVISION_ID   0x0066
 

The offset to the PPCI configuration revision ID register.

#define PPCI_CFG_STATUS2   0x0050
 

The offset to the PPCI configuration status register 2.

#define PPCI_CFG_STATUS2_MASK   0x0054
 

The offset to the PPCI configuration status interrupt mask register 2.

#define PPCI_CFG_USER_A   0x00c0
 

The offset to the PPCI user-defined register A.

#define PPCI_CFG_USER_B   0x00a8
 

The offset to the PPCI user-defined register B.

#define PPCI_CFG_USER_C   0x00ac
 

The offset to the PPCI user-defined register C.

#define PPCI_DEVICE_ID   0x0010
 

The PowerPCI configuration register Device ID value.

#define PPCI_ERR_CHK_ARB_CONTROL   0x0006
 

The PPCI PCI error checking register bit mask for bus arbitration latency timeout clock.

#define PPCI_ERR_CHK_ARB_TIMEOUT   0x0001
 

The PPCI PCI error checking register bit mask for bus arbitration latency error enable.

#define PPCI_ERR_CHK_DATA_CONTROL   0x0030
 

The PPCI PCI error checking register bit mask for bus data phase timeout clock.

#define PPCI_ERR_CHK_DATA_TIMEOUT   0x0008
 

The PPCI PCI error checking register bit mask for bus data phase timeout error enable.

#define PPCI_ERR_CHK_PROTOCOL   0x0400
 

The PPCI PCI error checking register bit mask for bus protocol error enable.

#define PPCI_ERR_CHK_RDY_PAR   0x0200
 

The PPCI PCI error checking register bit mask for bus ready signal parity error enable.

#define PPCI_VEC_60X_CRIT_ERR   0x40000000
 

The PPCI vector register 60X bus critical error bit mask.

#define PPCI_VEC_CAT_CRIT_ERR   0x00200000
 

The PPCI vector register clock and test critical error bit mask.

#define PPCI_VEC_CHECKSTOP   0x00004000
 

The PPCI vector register EMC checkstop bit mask.

#define PPCI_VEC_CPU_INT   0x00000400
 

The PPCI vector register CPU interrupt bit mask.

#define PPCI_VEC_EMC_CRIT_ERR   0x00800000
 

The PPCI vector register EMC critical error bit mask.

#define PPCI_VEC_JTAG_MAST_CRIT_ERR   0x20000000
 

The PPCI vector register JTAG master critical error bit mask.

#define PPCI_VEC_JTAG_MS_MAST_CRIT_ERR   0x10000000
 

The PPCI vector register JTAG master/slave master critical error bit mask.

#define PPCI_VEC_JTAG_MS_SLV_CRIT_ERR   0x08000000
 

The PPCI vector register JTAG master/slave slave critical error bit mask.

#define PPCI_VEC_MEM_CRIT_ERR   0x04000000
 

The PPCI vector register memory controller critical error bit mask.

#define PPCI_VEC_MISC_CRIT_ERR   0x00400000
 

The PPCI vector register MISC function critical error bit mask.

#define PPCI_VEC_OCB_CRIT_ERR   0x02000000
 

The PPCI vector register OCB critical error bit mask.

#define PPCI_VEC_PCI_CRIT_ERR   0x80000000
 

The PPCI vector register PCI critical error bit mask.

#define PPCI_VEC_TIMER_1   0x00002000
 

The PPCI vector register timer 1 expiration bit mask.

#define PPCI_VEC_TIMER_2   0x00001000
 

The PPCI vector register timer 1 expiration bit mask.

#define PPCI_VEC_TIMER_3   0x00000800
 

The PPCI vector register timer 1 expiration bit mask.

#define PPCI_VEC_UART_CRIT_ERR   0x01000000
 

The PPCI vector register UART critical error bit mask.

#define PPCI_VEC_WDT_EXPIRE   0x00008000
 

The PPCI vector register PPCI watchdog timer expiration bit mask.

#define PPCI_VENDOR_ID   0x11d0
 

The PowerPCI configuration register Vendor ID value.

#define USERC_ADDR_WAIT   0x0000000c
 

The PPCI user defined C register bit mask for 60X bus address wait states.

#define USERC_DBWO_ENABLE   0x00008000
 

The PPCI user defined C register bit mask for 60X bus DBWO enable.

#define USERC_FF0_LOCAL   0x04000000
 

The PPCI user defined C register bit mask for 60X SUROM location control.

#define USERC_NO_SNOOP_ENABLE   0x08000000
 

The PPCI user defined C register bit mask for 60X bus no snoop enable.

#define USERC_SNOOP_WAIT   0x000c0000
 

The PPCI user defined C register bit mask for 60X bus snoop wait states.

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