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sib.h File Reference

Hardware definitions for LAT SIB board. More...

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PCI Configuration Header Definitions

#define SIB_PCI_VENDOR_ID   0x11aa
#define SIB_PCI_DEVICE_ID   0x0844
#define SIB_EVAL_PCI_VENDOR_ID   0x11aa
#define SIB_EVAL_PCI_DEVICE_ID   0x0001

Memory Map Definitions

#define SIB_OFFSET_STATUS_REG   0x00000000
#define SIB_OFFSET_CONTROL_REG   0x00000004
#define SIB_OFFSET_PDU_GASU_REG   0x00000008
#define SIB_OFFSET_HEATER_REG   0x0000000c
#define SIB_OFFSET_WATCHDOG_REG   0x00000010
#define SIB_OFFSET_SUMMIT_REG   0x00400000
#define SIB_OFFSET_SUMMIT_MEM   0x00600000
#define SIB_OFFSET_EEPROM_LOWER   0x00800000
#define SIB_OFFSET_EEPROM_UPPER   0x00c00000
#define SIB_EVAL_OFFSET_STATUS_REG   0x00000000
#define SIB_EVAL_OFFSET_CONTROL_REG   0x00000004
#define SIB_EVAL_OFFSET_SUMMIT_REG   0x00800000
#define SIB_EVAL_OFFSET_SUMMIT_MEM   0x00c00000
#define SIB_EVAL_OFFSET_EEPROM_LOWER   0x00400000
#define SIB_EVAL_OFFSET_EEPROM_UPPER   0x00600000
#define SIB_OFFSET_INTR_REG   0x48
#define SIB_EVAL_OFFSET_INTR_REG   0x48

Memory Bank Size Definitions

#define SIB_SIZE_EEPROM_LOWER   0x00300000
#define SIB_SIZE_EEPROM_UPPER   0x00300000
#define SIB_EVAL_SIZE_EEPROM_LOWER   0x00180000
#define SIB_EVAL_SIZE_EEPROM_UPPER   0x00180000
#define SIB_SIZE_SUMMIT_MEM   0x00020000
#define SIB_EVAL_SIZE_SUMMIT_MEM   0x00020000

Status Register Bit Mask Definitions

#define SIB_STATUS_UEEP_WER   0x00000080
#define SIB_STATUS_LEEP_WER   0x00000040
#define SIB_STATUS_UEEP_WE   0x00000020
#define SIB_STATUS_LEEP_WE   0x00000010
#define SIB_STATUS_MISS_DPS   0x00000008
#define SIB_STATUS_WDT_TO   0x00000004
#define SIB_STATUS_READY   0x00000002
#define SIB_STATUS_TERMACT   0x00000001
#define SIB_EVAL_STATUS_UEEP_WER   0x00008000
#define SIB_EVAL_STATUS_LEEP_WER   0x00004000
#define SIB_EVAL_STATUS_UEEP_WE   0x00002000
#define SIB_EVAL_STATUS_LEEP_WE   0x00001000
#define SIB_EVAL_STATUS_MISS_DPS   0x00000800
#define SIB_EVAL_STATUS_READY   0x00000200
#define SIB_EVAL_STATUS_TERMACT   0x00000100

Control Register Bit Mask Definitions

#define SIB_CONTROL_SUM_RES   0x00000080
#define SIB_CONTROL_GSW_INTR   0x00000040
#define SIB_CONTROL_U_EPWE_LATCH   0x00000020
#define SIB_CONTROL_U_EPWE_SD   0x00000010
#define SIB_CONTROL_U_EPWE_INIT   0x00000008
#define SIB_CONTROL_L_EPWE_LATCH   0x00000004
#define SIB_CONTROL_L_EPWE_SD   0x00000002
#define SIB_CONTROL_L_EPWE_INIT   0x00000001
#define SIB_EVAL_CONTROL_SUM_RES   0x00000010
#define SIB_EVAL_CONTROL_GSW_INTR   0x00000008
#define SIB_EVAL_CONTROL_EPWE_LATCH   0x00000004
#define SIB_EVAL_CONTROL_EPWE_SD   0x00000002
#define SIB_EVAL_CONTROL_EPWE_INIT   0x00000001

Interrupt Register Bit Mask Definitions

#define SIB_INTR_STATUS   0x00000100
#define SIB_INTR_ENABLE   0x00000200
#define SIB_EVAL_INTR_STATUS   0x00000100
#define SIB_EVAL_INTR_ENABLE   0x00000200

Heater Control Register Bit Mask Definitions

#define SIB_HEATER_RH_1_OFF   0x00000001
#define SIB_HEATER_RH_2_OFF   0x00000002
#define SIB_HEATER_RH_3_OFF   0x00000004
#define SIB_HEATER_RH_4_OFF   0x00000008
#define SIB_HEATER_RH_5_OFF   0x00000010
#define SIB_HEATER_RH_6_OFF   0x00000020
#define SIB_HEATER_LH_1_OFF   0x00000100
#define SIB_HEATER_LH_2_OFF   0x00000200
#define SIB_HEATER_LH_3_OFF   0x00000400
#define SIB_HEATER_LH_4_OFF   0x00000800
#define SIB_HEATER_LH_5_OFF   0x00001000
#define SIB_HEATER_LH_6_OFF   0x00002000

PDU/GASU Control Register Bit Masks

#define SIB_PDU_GRON   0x00000001
#define SIB_PDU_GPON   0x00000002
#define SIB_PDU_PRON   0x00000004
#define SIB_PDU_PPON   0x00000008
#define SIB_PDU_SPPSEL   0x00000010
#define SIB_PDU_SPARE_0   0x00000020
#define SIB_PDU_SPARE_1   0x00000040
#define SIB_PDU_SPARE_2   0x00000080
#define SIB_PDU_SPARE_3   0x00000100

Detailed Description

Hardware definitions for LAT SIB board.

This header contains definitions for the LAT SIB board. Definitions for both the evaluation board design and the flight board design are present. Definitions for the evaluation board (vendor ID = 0x11aa, device ID = 0x0001) are prefixed with "SIB_EVAL_". Definitions for the flight board (vendor ID = 0x11aa, device ID = 0x0844) are prefixed with simply "SIB_".

Define Documentation

#define SIB_CONTROL_GSW_INTR   0x00000040
 

The bit mask definition for the SIB board control register generate software interrupt bit.

#define SIB_CONTROL_L_EPWE_INIT   0x00000001
 

The bit mask definition for the SIB board control register lower EEPROM key initialize bit.

#define SIB_CONTROL_L_EPWE_LATCH   0x00000004
 

The bit mask definition for the SIB board control register lower EEPROM key latch bit.

#define SIB_CONTROL_L_EPWE_SD   0x00000002
 

The bit mask definition for the SIB board control register lower EEPROM key serial data bit.

#define SIB_CONTROL_SUM_RES   0x00000080
 

The bit mask definition for the SIB board control register Summit hardware reset bit.

#define SIB_CONTROL_U_EPWE_INIT   0x00000008
 

The bit mask definition for the SIB board control register upper EEPROM key initialize bit.

#define SIB_CONTROL_U_EPWE_LATCH   0x00000020
 

The bit mask definition for the SIB board control register upper EEPROM key latch bit.

#define SIB_CONTROL_U_EPWE_SD   0x00000010
 

The bit mask definition for the SIB board control register upper EEPROM key serial data bit.

#define SIB_EVAL_CONTROL_EPWE_INIT   0x00000001
 

The bit mask definition for the SIB evaluation board control register upper EEPROM key initialize bit.

#define SIB_EVAL_CONTROL_EPWE_LATCH   0x00000004
 

The bit mask definition for the SIB evaluation board control register upper EEPROM key latch bit.

#define SIB_EVAL_CONTROL_EPWE_SD   0x00000002
 

The bit mask definition for the SIB evaluation board control register upper EEPROM key serial data bit.

#define SIB_EVAL_CONTROL_GSW_INTR   0x00000008
 

The bit mask definition for the SIB evaluation board control register generate software interrupt bit.

#define SIB_EVAL_CONTROL_SUM_RES   0x00000010
 

The bit mask definition for the SIB evaluation board control register Summit hardware reset bit.

#define SIB_EVAL_INTR_ENABLE   0x00000200
 

The bit mask definition for the SIB evaluation board interrupt register interrupt enable bit.

#define SIB_EVAL_INTR_STATUS   0x00000100
 

The bit mask definition for the SIB evaluation board interrupt register interrupt status bit.

#define SIB_EVAL_OFFSET_CONTROL_REG   0x00000004
 

The offset in bytes from the BAR0 address to the SIB evaluation board control register.

#define SIB_EVAL_OFFSET_EEPROM_LOWER   0x00400000
 

The offset in bytes from the BAR0 address to the SIB evaluation board EEPROM lower bank.

#define SIB_EVAL_OFFSET_EEPROM_UPPER   0x00600000
 

The offset in bytes from the BAR0 address to the SIB evaluation board EEPROM upper bank.

#define SIB_EVAL_OFFSET_INTR_REG   0x48
 

The offset in bytes into the PCI configuration space to the SIB evaluation board interrupt register.

#define SIB_EVAL_OFFSET_STATUS_REG   0x00000000
 

The offset in bytes from the BAR0 address to the SIB evaluation board status register.

#define SIB_EVAL_OFFSET_SUMMIT_MEM   0x00c00000
 

The offset in bytes from the BAR0 address to the SIB evaluation board Summit shared memory.

#define SIB_EVAL_OFFSET_SUMMIT_REG   0x00800000
 

The offset in bytes from the BAR0 address to the SIB evaluation board Summit controller registers.

#define SIB_EVAL_PCI_DEVICE_ID   0x0001
 

The PCI configuration header Device ID for the SIB evaluation board.

#define SIB_EVAL_PCI_VENDOR_ID   0x11aa
 

The PCI configuration header Vendor ID for the SIB evaluation board.

#define SIB_EVAL_SIZE_EEPROM_LOWER   0x00180000
 

The size in bytes of the SIB evaluation board EEPROM lower bank.

#define SIB_EVAL_SIZE_EEPROM_UPPER   0x00180000
 

The size in bytes of the SIB evaluation board EEPROM upper bank.

#define SIB_EVAL_SIZE_SUMMIT_MEM   0x00020000
 

The size in bytes of the SIB evaluation board Summit shared memory.

#define SIB_EVAL_STATUS_LEEP_WE   0x00001000
 

The bit mask definition for the SIB evaluation board status register lower EEPROM write enable bit.

#define SIB_EVAL_STATUS_LEEP_WER   0x00004000
 

The bit mask definition for the SIB evaluation board status register lower EEPROM write error bit.

#define SIB_EVAL_STATUS_MISS_DPS   0x00000800
 

The bit mask definition for the SIB evaluation board status register data phase error bit.

#define SIB_EVAL_STATUS_READY   0x00000200
 

The bit mask definition for the SIB evaluation board status register Summit ready bit.

#define SIB_EVAL_STATUS_TERMACT   0x00000100
 

The bit mask definition for the SIB evaluation board status register Summit terminal active bit.

#define SIB_EVAL_STATUS_UEEP_WE   0x00002000
 

The bit mask definition for the SIB evaluation board status register upper EEPROM write enable bit.

#define SIB_EVAL_STATUS_UEEP_WER   0x00008000
 

The bit mask definition for the SIB evaluation board status register upper EEPROM write error bit.

#define SIB_HEATER_LH_1_OFF   0x00000100
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_LH_2_OFF   0x00000200
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_LH_3_OFF   0x00000400
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_LH_4_OFF   0x00000800
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_LH_5_OFF   0x00001000
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_LH_6_OFF   0x00002000
 

Bit mask for SIB heater control register left heater 7 off.

#define SIB_HEATER_RH_1_OFF   0x00000001
 

Bit mask for SIB heater control register right heater 1 off.

#define SIB_HEATER_RH_2_OFF   0x00000002
 

Bit mask for SIB heater control register right heater 2 off.

#define SIB_HEATER_RH_3_OFF   0x00000004
 

Bit mask for SIB heater control register right heater 3 off.

#define SIB_HEATER_RH_4_OFF   0x00000008
 

Bit mask for SIB heater control register right heater 4 off.

#define SIB_HEATER_RH_5_OFF   0x00000010
 

Bit mask for SIB heater control register right heater 5 off.

#define SIB_HEATER_RH_6_OFF   0x00000020
 

Bit mask for SIB heater control register right heater 6 off.

#define SIB_INTR_ENABLE   0x00000200
 

The bit mask definition for the SIB board interrupt register interrupt enable bit.

#define SIB_INTR_STATUS   0x00000100
 

The bit mask definition for the SIB board interrupt register interrupt status bit.

#define SIB_OFFSET_CONTROL_REG   0x00000004
 

The offset in bytes from the BAR0 address to the SIB board control register.

#define SIB_OFFSET_EEPROM_LOWER   0x00800000
 

The offset in bytes from the BAR0 address to the SIB board EEPROM lower bank.

#define SIB_OFFSET_EEPROM_UPPER   0x00c00000
 

The offset in bytes from the BAR0 address to the SIB board EEPROM upper bank.

#define SIB_OFFSET_HEATER_REG   0x0000000c
 

The offset in bytes from the BAR0 address to the SIB board heater control register.

#define SIB_OFFSET_INTR_REG   0x48
 

The offset in bytes into the PCI configuration space to the SIB board interrupt register.

#define SIB_OFFSET_PDU_GASU_REG   0x00000008
 

The offset in bytes from the BAR0 address to the SIB board PDU/GASU control register.

#define SIB_OFFSET_STATUS_REG   0x00000000
 

The offset in bytes from the BAR0 address to the SIB board status register.

#define SIB_OFFSET_SUMMIT_MEM   0x00600000
 

The offset in bytes from the BAR0 address to the SIB board Summit shared memory.

#define SIB_OFFSET_SUMMIT_REG   0x00400000
 

The offset in bytes from the BAR0 address to the SIB board Summit controller registers.

#define SIB_OFFSET_WATCHDOG_REG   0x00000010
 

The offset in bytes from the BAR0 address to the SIB watchdog timer register.

#define SIB_PCI_DEVICE_ID   0x0844
 

The PCI configuration header Device ID for the SIB board.

#define SIB_PCI_VENDOR_ID   0x11aa
 

The PCI configuration header Vendor ID for the SIB board.

#define SIB_PDU_GPON   0x00000002
 

The bit mask for the PDU/GASU register GASU primary on.

#define SIB_PDU_GRON   0x00000001
 

The bit mask for the PDU/GASU register GASU redundant on.

#define SIB_PDU_PPON   0x00000008
 

The bit mask for the PDU/GASU register PDU primary on.

#define SIB_PDU_PRON   0x00000004
 

The bit mask for the PDU/GASU register PDU redundant on.

#define SIB_PDU_SPARE_0   0x00000020
 

The bit mask for the PDU/GASU register PDU spare discrete 0.

#define SIB_PDU_SPARE_1   0x00000040
 

The bit mask for the PDU/GASU register PDU spare discrete 0.

#define SIB_PDU_SPARE_2   0x00000080
 

The bit mask for the PDU/GASU register PDU spare discrete 0.

#define SIB_PDU_SPARE_3   0x00000100
 

The bit mask for the PDU/GASU register PDU spare discrete 0.

#define SIB_PDU_SPPSEL   0x00000010
 

The bit mask for the PDU/GASU register SC power primary select.

#define SIB_SIZE_EEPROM_LOWER   0x00300000
 

The size in bytes of the SIB board EEPROM lower bank.

#define SIB_SIZE_EEPROM_UPPER   0x00300000
 

The size in bytes of the SIB board EEPROM upper bank.

#define SIB_SIZE_SUMMIT_MEM   0x00020000
 

The size in bytes of the SIB board Summit shared memory.

#define SIB_STATUS_LEEP_WE   0x00000010
 

The bit mask definition for the SIB board status register lower EEPROM write enable bit.

#define SIB_STATUS_LEEP_WER   0x00000040
 

The bit mask definition for the SIB board status register lower EEPROM write error bit.

#define SIB_STATUS_MISS_DPS   0x00000008
 

The bit mask definition for the SIB board status register data phase error bit.

#define SIB_STATUS_READY   0x00000002
 

The bit mask definition for the SIB board status register Summit ready bit.

#define SIB_STATUS_TERMACT   0x00000001
 

The bit mask definition for the SIB board status register Summit terminal active bit.

#define SIB_STATUS_UEEP_WE   0x00000020
 

The bit mask definition for the SIB board status register upper EEPROM write enable bit.

#define SIB_STATUS_UEEP_WER   0x00000080
 

The bit mask definition for the SIB board status register upper EEPROM write error bit.

#define SIB_STATUS_WDT_TO   0x00000004
 

The bit mask definition for the SIB board status register watchdog timeout bit.

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