---

GLAST / LAT > DAQ and FSW > FSW > Doxygen Index> VXW / V7-2-0 > vxw_flight / rad750

---

         

---

_isrRoutingInfo Struct Reference

#include <isrRouter.h>

List of all members.

Public Attributes
isrTableEntry_t	isrTable [MAX_INT_LEVELS]
regPtr_t	pStatusReg
regPtr_t	pEnableReg
BOOL	clear
BOOL	one_pass

---

Detailed Description

----------------------------------------------------------------------------

ISR look-up table structures

The underlying hardware is assumed to have the following proerties:

• Interrupt Status reg - A 32-bit reg where each bit set indicates an active interrupt.
• Interrupt Enable reg - A 32-bit reg where each bit set indicates an enabled interrupt. This reg is also assumed to be 'write to clear,' i.e., any bit can be cleared by writing a 1 to that bit. This only needs to be the case if the 'clear' BOOL is true.
• These regs are ANDed together and then bit by bit ORed to produce a signal which triggers the interrupt router to gain control.
• Both of these regs can be acceessed via direct PIO (pointer reference).
• Both of these regs must be byte-swapped.

----------------------------------------------------------------------------

---

Member Data Documentation

isrTableEntry_t _isrRoutingInfo::isrTable[MAX_INT_LEVELS]

ISR look-up table

regPtr_t _isrRoutingInfo::pStatusReg

Pointer to int status reg

regPtr_t _isrRoutingInfo::pEnableReg

Pointer to in enable reg

BOOL _isrRoutingInfo::clear

Should int status be cleared?

BOOL _isrRoutingInfo::one_pass

Just read regs once?

---

The documentation for this struct was generated from the following file:

• isrRouter.h

---