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Defines | |
RAD750 Hardware Memory Map Definitions | |
These addresses and sizes are fixed and determined by the RAD750 hardware. | |
| #define | MEMMAP_RAM_LOGICAL_BASE (0x00000000) |
| Logical address for RAD750 SDRAM. | |
| #define | MEMMAP_RAM_PHYSICAL_BASE (MEMMAP_RAM_LOGICAL_BASE) |
| Physical address on the OCB for RAD750 SDRAM. | |
| #define | MEMMAP_RAM_PHYSICAL_BYTES (0x08000000) |
| Size of RAD750 SDRAM. | |
| #define | MEMMAP_PCI_LOGICAL_BASE (0x80000000) |
| Logical address for RAD750 PCI I/O address space. | |
| #define | MEMMAP_PCI_PHYSICAL_BASE (MEMMAP_PCI_LOGICAL_BASE) |
| Physical address on the OCB for PCI I/O address space. | |
| #define | MEMMAP_PPCI_LOGICAL_BASE (0xBF800000) |
| Logical address for RAD750 Power-PCI registers. | |
| #define | MEMMAP_PPCI_PHYSICAL_BASE (MEMMAP_PPCI_LOGICAL_BASE) |
| Physical address on the OCB for Power-PCI registers. | |
| #define | MEMMAP_PCI_MEM_LOGICAL_BASE (0xC0000000) |
| Logical address for RAD750 PCI memory address space. | |
| #define | MEMMAP_PCI_MEM_PHYSICAL_BASE (MEMMAP_PCI_MEM_LOGICAL_BASE) |
| Physical address on the OCB for PCI memory address space. | |
| #define | MEMMAP_ROM_LOGICAL_BASE (0xFFF00000) |
| Logical address for RAD750 Boot ROM (SUROM). | |
| #define | MEMMAP_ROM_PHYSICAL_BASE (MEMMAP_ROM_LOGICAL_BASE) |
| Logical address for RAD750 Boot ROM (SUROM). Defines the physical address on the OCB for RAD750 Boot ROM (SUROM). | |
| #define | MEMMAP_ROM_PHYSICAL_BYTES (0x00040000) |
| Size of RAD750 Boot ROM (SUROM). | |
SUROM Boot Memory Map Definitions | |
These addresses and sizes describe regions of the memory map that are located within the boot ROM (SUROM). Only those regions used directly by the RTOS are described here. | |
| #define | MEMMAP_ROM_PPC_RESET_ADRS (0xFFF00100) |
| Location of start of ROM-based PPC reset handler region. | |
SDRAM Boot Memory Map Definitions | |
These addresses and sizes describe regions of the memory map that are located within the SDRAM and available to the primary boot code (PBC). Only those regions used directly by the RTOS are described here. | |
| #define | MEMMAP_RAM_BOOT_BASE (0x00000000) |
| Location of start of memory available to PBC. | |
| #define | MEMMAP_RAM_BOOT_BYTES (0x00C00000) |
| Size of memory available to PBC. | |
| #define | MEMMAP_APPLICATION_BASE (0x00C00000) |
| Location of application SDRAM. | |
| #define | MEMMAP_APPLICATION_BYTES (0x07400000) |
| Size of application SDRAM region. | |
| #define | MEMMAP_RAM_RTOS_BOOT_LINE_ADRS (0x0000FD00) |
| Address in RAM of the RTOS boot line. | |
| #define | MEMMAP_RAM_RTOS_BOOT_LINE_BYTES (0x00000100) |
| Size in RAM of the RTOS boot line region. | |
| #define | MEMMAP_RAM_RTOS_EXC_MSG_ADRS (0x0000FE00) |
| Address in RAM of the RTOS exception message. | |
| #define | MEMMAP_RAM_RTOS_EXC_MSG_BYTES (0x00000100) |
| Size in RAM of the RTOS exception message region. | |
| #define | MEMMAP_EMC_PARAM_ADRS (0x0000FF00) |
| Address in RAM of shared EMC/PPC parameters. | |
| #define | MEMMAP_EMC_PARAM_SIZE (0x00000080) |
| Size of shared EMC/PPC parameter area. | |
| #define | MEMMAP_BOOT_DIAGS_ADDR (0x0000FF80) |
| Location of boot diagnostics region. | |
| #define | MEMMAP_BOOT_DIAGS_BYTES (0x00000080) |
| Size of boot diagnostics region. | |
| #define | MEMMAP_SBC_RAM_MOD0_ADRS (0x00010000) |
| Address in RAM of SBC Module 0 region in RAM. | |
| #define | MEMMAP_SBC_RAM_MOD0_SIZE (0x00060000) |
| Size in RAM of SBC Module 0 region in RAM. | |
| #define | MEMMAP_SBC_RAM_MOD1_ADRS (0x00070000) |
| Address in RAM of SBC Module 1 region in RAM. | |
| #define | MEMMAP_SBC_RAM_MOD1_SIZE (0x00010000) |
| Size in RAM of SBC Module 1 region in RAM. | |
| #define | MEMMAP_SBC_RAM_RTOS_ADRS (0x00300000) |
| Address in RAM of SBC RTOS region in RAM. | |
| #define | MEMMAP_SBC_RAM_RTOS_SIZE (0x00900000) |
| Size in RAM of SBC RTOS region in RAM. | |
SIB EEPROM Boot Memory Map Definitions | |
These offsets and sizes describe regions of the SIB board EEPROM banks and are available to the primary boot code (PBC). | |
| #define | MEMMAP_BHDR_BASE_OFFSET (0x00000000) |
| EEPROM bank header offset. | |
| #define | MEMMAP_BHDR_SIZE (256) |
| Size of EEPROM bank header. | |
| #define | MEMMAP_BHDR_CHECKSUM_OFFSET (0x00000000) |
| Bank header checksum offset. | |
| #define | MEMMAP_BHDR_RTOS_PTR_OFFSET (0x00000004) |
| Bank header RTOS pointer offset. | |
| #define | MEMMAP_BHDR_RTOS_SIZE_OFFSET (0x00000008) |
| Bank header RTOS size offset. | |
| #define | MEMMAP_BHDR_SEG0_PTR_OFFSET (0x0000000C) |
| Bank header SEG0 pointer offset. | |
| #define | MEMMAP_BHDR_SEG0_SIZE_OFFSET (0x00000010) |
| Bank header SEG0 size offset. | |
| #define | MEMMAP_BHDR_SEG1_PTR_OFFSET (0x00000014) |
| Bank header SEG1 pointer offset. | |
| #define | MEMMAP_BHDR_SEG1_SIZE_OFFSET (0x00000018) |
| Bank header SEG1 size offset. | |
| #define | MEMMAP_BHDR_NVRAM_PTR_OFFSET (0x0000001C) |
| Bank header NVRAM pointer offset. | |
| #define | MEMMAP_BHDR_NVRAM_SIZE_OFFSET (0x00000020) |
| Bank header NVRAM size offset. | |
| #define | MEMMAP_BHDR_RESET_PTR_OFFSET (0x00000024) |
| Offset of turbo-reset database. | |
| #define | MEMMAP_BHDR_RESET_SIZE_OFFSET (0x00000028) |
| Offset of turbo-reset database. | |
| #define | MEMMAP_TFFS_SEGMENT_OFFSET (0x00100000) |
| Offset of TFFS filesystem. | |
Revision 1.10 2005/01/12 16:36:57 dmay increase SUROM size back to 256KB
Revision 1.9 2004/09/03 20:40:23 dmay reduced SUROM size to 64K; removed PBC-specific definitions
Revision 1.8 2004/06/14 14:24:41 dmay Change memory map to start RTOS at 0030.0000 and reserve 9MB for its use
Revision 1.7 2004/05/21 16:52:34 dwood Added doxygen section markers to make output more legible.
Revision 1.6 2004/05/12 19:46:03 dmay Filled in the memory map, removed MEMMAP_SIB_EEPROM_BYTES, added consistency checks
Revision 1.5 2004/03/18 15:45:22 ray added RAM RTOS load region defs, fixed a few typos
Revision 1.4 2003/11/19 13:35:26 ray updates to boot diagnostics and memory map
Revision 1.3 2003/11/05 19:29:45 dwood Fixed typo for macro name.
Revision 1.2 2003/10/31 19:37:25 ray update BOOT EEPROM Header Size to 256
Revision 1.1 2003/10/16 12:07:36 ray initial revision of rad750 memory map
| #define MEMMAP_APPLICATION_BASE (0x00C00000) |
Location of application SDRAM.
Defines the logical address in SDRAM reserved for use by the GLAST applications. This is RAM not availble for use by PBC or SBC.
| #define MEMMAP_APPLICATION_BYTES (0x07400000) |
Size of application SDRAM region.
Defines the amount of SDRAM (in bytes) that makes up the application region.
| #define MEMMAP_BHDR_BASE_OFFSET (0x00000000) |
EEPROM bank header offset.
Offset in bytes from start of EEPROM bank to bank header.
| #define MEMMAP_BHDR_CHECKSUM_OFFSET (0x00000000) |
Bank header checksum offset.
Offset (in bytes) in EEPROM bank header to bank header checksum.
| #define MEMMAP_BHDR_NVRAM_PTR_OFFSET (0x0000001C) |
Bank header NVRAM pointer offset.
Offset (in bytes) in EEPROM bank header to where the NVRAM pointer is stored. The NVRAM pointer is itself an offset from the EEPROM bank to where the NVRAM contents are stored.
Referenced by main().
| #define MEMMAP_BHDR_NVRAM_SIZE_OFFSET (0x00000020) |
Bank header NVRAM size offset.
Offset (in bytes) in EEPROM bank header to NVRAM contents size.
Referenced by main().
| #define MEMMAP_BHDR_RESET_PTR_OFFSET (0x00000024) |
Offset of turbo-reset database.
Offset (bytes) into EEPROM bank header to a location where a pointer to the RESET database is stored. The data stored in this location is itself an offset from the EEPROM bank header to where the RESET database is located.
Referenced by main().
| #define MEMMAP_BHDR_RESET_SIZE_OFFSET (0x00000028) |
Offset of turbo-reset database.
Offset (bytes) into EEPROM bank header where the maximum allowed size of the RESET database is stored.
Referenced by main().
| #define MEMMAP_BHDR_RTOS_PTR_OFFSET (0x00000004) |
Bank header RTOS pointer offset.
Offset (in bytes) in EEPROM bank header to where the RTOS pointer is stored. The RTOS pointer is itself an offset from the EEPROM bank to where the RTOS file is stored.
Referenced by main().
| #define MEMMAP_BHDR_RTOS_SIZE_OFFSET (0x00000008) |
Bank header RTOS size offset.
Offset (in bytes) in EEPROM bank header to RTOS file size.
Referenced by main().
| #define MEMMAP_BHDR_SEG0_PTR_OFFSET (0x0000000C) |
Bank header SEG0 pointer offset.
Offset (in bytes) in EEPROM bank header to where the SEG0 pointer is stored. The SEG0 pointer is itself an offset from the EEPROM bank to where the load segment 0 file is stored.
Referenced by main().
| #define MEMMAP_BHDR_SEG0_SIZE_OFFSET (0x00000010) |
Bank header SEG0 size offset.
Offset (in bytes) in EEPROM bank header to SEG0 file size.
Referenced by main().
| #define MEMMAP_BHDR_SEG1_PTR_OFFSET (0x00000014) |
Bank header SEG1 pointer offset.
Offset (in bytes) in EEPROM bank header to where the SEG1 pointer is stored. The SEG1 pointer is itself an offset from the EEPROM bank to where the load segment 1 file is stored.
Referenced by main().
| #define MEMMAP_BHDR_SEG1_SIZE_OFFSET (0x00000018) |
Bank header SEG1 size offset.
Offset (in bytes) in EEPROM bank header to SEG1 file size.
Referenced by main().
| #define MEMMAP_BHDR_SIZE (256) |
| #define MEMMAP_BOOT_DIAGS_ADDR (0x0000FF80) |
Location of boot diagnostics region.
Defines the logical address in SDRAM where the boot diagnostics data is kept. This area provides a section of memory that the primary boot, secondary boot and the application code can use to communicate flags and status during the boot stages. Primary and secondary boot flags are stored here, along with memory test results, and reset sources.
| #define MEMMAP_BOOT_DIAGS_BYTES (0x00000080) |
Size of boot diagnostics region.
Defines the amount of SDRAM (in bytes) that is used for the boot diagnostics data.
| #define MEMMAP_EMC_PARAM_ADRS (0x0000FF00) |
Address in RAM of shared EMC/PPC parameters.
Defines the address in RAM where the EMC expects any parameters to be located for the CPU requests to the EMC. The EMC code defines the format and layout of these parameters as such:
For the Set Clock Command, the PPC sets the following:
0x0000FF00: 0x0000FADE 0x0000FF08: 32-bit value for PLL Setup register 0x0000FF0C: 32-bit value for PLL Configuration register 0x0000FF04: Method - 0 = Reset method, non-zero = sleep method
The EMC responds by setting address 0x0000FF00 to 0x0000DEED on success or 0x0000BADC on failure.
| #define MEMMAP_EMC_PARAM_SIZE (0x00000080) |
Size of shared EMC/PPC parameter area.
Defines the size (in bytes) of the shared area in RAM where the EMC and PPC share parameters.
| #define MEMMAP_PCI_LOGICAL_BASE (0x80000000) |
Logical address for RAD750 PCI I/O address space.
Defines the logical address for RAD750 PCI I/O address space. We don't re-map the address, so it is the same as the physical address.
| #define MEMMAP_PCI_MEM_LOGICAL_BASE (0xC0000000) |
Logical address for RAD750 PCI memory address space.
Defines the logical address for RAD750 PCI memory address space. We don't re-map the address, so it is the same as the physical address.
| #define MEMMAP_PCI_MEM_PHYSICAL_BASE (MEMMAP_PCI_MEM_LOGICAL_BASE) |
Physical address on the OCB for PCI memory address space.
Defines the physical address on the OCB for PCI memory address space.
| #define MEMMAP_PCI_PHYSICAL_BASE (MEMMAP_PCI_LOGICAL_BASE) |
Physical address on the OCB for PCI I/O address space.
Defines the physical address on the OCB for PCI I/O address space.
| #define MEMMAP_PPCI_LOGICAL_BASE (0xBF800000) |
Logical address for RAD750 Power-PCI registers.
Defines the logical address for RAD750 Power-PCI registers. We don't re-map the address, so it is the same as the physical address.
| #define MEMMAP_PPCI_PHYSICAL_BASE (MEMMAP_PPCI_LOGICAL_BASE) |
Physical address on the OCB for Power-PCI registers.
Defines the physical address on the OCB for Power-PCI registers.
| #define MEMMAP_RAM_BOOT_BASE (0x00000000) |
Location of start of memory available to PBC.
Defines the logical address in SDRAM that is the start of the region available to the Primary Boot Code. Primary boot code will not use memory outside of this region.
| #define MEMMAP_RAM_BOOT_BYTES (0x00C00000) |
Size of memory available to PBC.
Defines the amount of SDRAM (in bytes) that is available to the Primary Boot Code.
| #define MEMMAP_RAM_LOGICAL_BASE (0x00000000) |
Logical address for RAD750 SDRAM.
Defines the logical address for RAD750 SDRAM. We don't re-map the address, so it is the same as the physical address.
| #define MEMMAP_RAM_PHYSICAL_BASE (MEMMAP_RAM_LOGICAL_BASE) |
Physical address on the OCB for RAD750 SDRAM.
Defines the physical address on the OCB for RAD750 SDRAM.
| #define MEMMAP_RAM_PHYSICAL_BYTES (0x08000000) |
Size of RAD750 SDRAM.
Defines the physical size (in bytes) of RAD750 SDRAM.
| #define MEMMAP_RAM_RTOS_BOOT_LINE_ADRS (0x0000FD00) |
Address in RAM of the RTOS boot line.
Defines an address in RAM where the RTOS stores its boot line.
| #define MEMMAP_RAM_RTOS_BOOT_LINE_BYTES (0x00000100) |
Size in RAM of the RTOS boot line region.
Defines the size (in bytes) of the RTOS boot line region in RAM. This is not the size of the boot line, but the size of the region allocated for its use.
| #define MEMMAP_RAM_RTOS_EXC_MSG_ADRS (0x0000FE00) |
Address in RAM of the RTOS exception message.
Defines an address in RAM where the RTOS stores an exception message.
| #define MEMMAP_RAM_RTOS_EXC_MSG_BYTES (0x00000100) |
Size in RAM of the RTOS exception message region.
Defines the size (in bytes) of the RTOS exception message region in RAM. This is not the size of the exception message, but the size of the region allocated for its use.
| #define MEMMAP_ROM_LOGICAL_BASE (0xFFF00000) |
Logical address for RAD750 Boot ROM (SUROM).
Defines the logical address for RAD750 Boot ROM (SUROM). We don't re-map the address, so it is the same as the physical address.
| #define MEMMAP_ROM_PHYSICAL_BYTES (0x00040000) |
Size of RAD750 Boot ROM (SUROM).
Defines the physical size (in bytes) of RAD750 Boot ROM (SUROM).
| #define MEMMAP_ROM_PPC_RESET_ADRS (0xFFF00100) |
Location of start of ROM-based PPC reset handler region.
Defines the address in ROM that is the start of the PPC reset handler region (aka the System Reset Exception Vector). The PPC begins program execution at this location following a reset. If a 'soft' reset occurs after the PPC has transitioned to operating from RAM, however, this region will not be used. Instead, the reset handler region located in RAM will be used.
| #define MEMMAP_SBC_RAM_MOD0_ADRS (0x00010000) |
Address in RAM of SBC Module 0 region in RAM.
Defines an address in RAM where the module 0 load for the secondary boot is located. The PBC loads code to this address to be loaded by the SBC if BOOT_DIAGS_SBF_FLAG_MOD0_SOURCE is cleared in the secondary boot flags.
| #define MEMMAP_SBC_RAM_MOD0_SIZE (0x00060000) |
Size in RAM of SBC Module 0 region in RAM.
Defines the size (in bytes) of the SBC Module 0 region in RAM. This is not the size of the module loaded in the module 0 region, but the size of the entire region.
| #define MEMMAP_SBC_RAM_MOD1_ADRS (0x00070000) |
Address in RAM of SBC Module 1 region in RAM.
Defines an address in RAM where a module 1 load for the secondary boot is located. The PBC loads code to this address to be loaded by the SBC if BOOT_DIAGS_SBF_FLAG_MOD1_SOURCE is cleared in the secondary boot flags.
| #define MEMMAP_SBC_RAM_MOD1_SIZE (0x00010000) |
Size in RAM of SBC Module 1 region in RAM.
Defines the size (in bytes) of the SBC Module 1 region in RAM. This is not the size of the module loaded in the module 1 region, but the size of the entire region.
| #define MEMMAP_SBC_RAM_RTOS_ADRS (0x00300000) |
Address in RAM of SBC RTOS region in RAM.
Defines an address in RAM where the RTOS load for the secondary boot is located. The PBC loads code to this address to be loaded by the SBC if BOOT_DIAGS_SBF_FLAG_RTOS_SOURCE is cleared in the secondary boot flags.
| #define MEMMAP_SBC_RAM_RTOS_SIZE (0x00900000) |
Size in RAM of SBC RTOS region in RAM.
Defines the size (in bytes) of the SBC RTOS region in RAM. This is not the size of the module loaded in the RTOS region, but the size of the entire region.
| #define MEMMAP_TFFS_SEGMENT_OFFSET (0x00100000) |
Offset of TFFS filesystem.
Offset into either EEPROM bank where the TFFS (FAT) file system starts.
1.5.8