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generate_xml.c File Reference

Program to generate some XML files to use for testing. More...

#include <stdlib.h>
#include <stdio.h>
#include <string.h>

Include dependency graph for generate_xml.c:


Data Structures

struct  Simple_register
 Structure to hold 32-bit register details. More...
struct  Short_register
 Structure to hold 16-bit register details. More...
struct  Long_register
 Structure to hold 64-bit register details. More...
struct  TAM_engine
 Structure to hold the values of the fields of a TAM engine register. More...
struct  ROI_register
 Structure to hold the values of the fields of an ROI register. More...
struct  TIE_register
 Structure to hold the name and value of a TIE register. More...
struct  SCH_register
 Structure to hold the name and value of a SCH register. More...
struct  CCC_register
struct  CRC_register
struct  TEM_register

Defines

#define CHECK_CALL(fn)   {if(fn) return fn;}
 Check the value of a function return code.

Enumerations

enum  {
  N_TWR = 2,
  N_CABLE = 2,
  N_READOUT = 2,
  N_TEM_REGISTER = 3,
  N_TIC_REGISTER = 4,
  N_CCC_REGISTER = 4,
  N_CRC_REGISTER = 5,
  N_CFE_REGISTER = 7,
  N_TCC_REGISTER = 3,
  N_AEM_REGISTER = 2,
  N_TAM_ENGINE = 16,
  N_ROI_REGISTER = 54,
  N_TIE_REGISTER = 18,
  N_SCH_REGISTER = 16
}
enum  {
  TAM_FIXED = 0x40000000,
  TAM_MBZ = 0x00007f00
}

Functions

int generate (const char *filename, const char *type)
 Generate the XML files.
void generate_GEM (FILE *fp)
 Generate a GEM XML file.
void generate_AEM (FILE *fp)
 Generate an AEM XML file.
void generate_TEM (FILE *fp)
 Generate a TEM XML file.
void generate_ACD (FILE *fp)
void generate_TKR (FILE *fp)
 Generate a TKR XML file.
void generate_CAL (FILE *fp)
 Generate a CAL XML file.
void generate_MAP (FILE *fp)
 Generate a map XML file.
int main (int argc, char **argv)
 Generate all the XML files used by the QCFG tests.

Variables

static const Simple_register dft_ccc [N_CCC_REGISTER]
static const Simple_register dft_crc [N_CRC_REGISTER]
static const Simple_register dft_cfe [N_CFE_REGISTER]
static const Simple_register dft_tcc [N_TCC_REGISTER]
static const CCC_register ccc [N_CABLE]
static const Simple_register dft_tem [N_TEM_REGISTER]
static const Simple_register dft_tic [N_TIC_REGISTER]
static const TEM_register tem [N_TWR]
static const Simple_register tic [N_TWR][N_TIC_REGISTER]
static const Simple_register aem [N_AEM_REGISTER]
static const TAM_engine engine [N_TAM_ENGINE]
static const ROI_register roi [N_ROI_REGISTER]
static const TIE_register tie [N_TIE_REGISTER]
static const SCH_register sch [N_SCH_REGISTER]
static const unsigned win_width = 0x5

Detailed Description

Program to generate some XML files to use for testing.

Author:
James Swain & Owen Saxton
Id
generate_xml.c,v 1.2 2007/03/16 23:51:06 saxton Exp

Function Documentation

int generate (  const char *  filename,
const char *  type
) 
 

Generate the XML files.

Use the values declared earlier to write out an XML file that can be processed by qcfg_parser to generate RIM binary files and a configuration master.

Parameters:
filename Name to use for the XML file generated
type Type of XML file to generate (GEM, AEM, TEM)
Returns:
0 on success or -1 if file open failed

void generate_AEM (  FILE *  fp  ) 
 

Generate an AEM XML file.

Parameters:
fp Pointer to opened file

void generate_CAL (  FILE *  fp  ) 
 

Generate a CAL XML file.

Parameters:
fp Pointer to opened file

void generate_GEM (  FILE *  fp  ) 
 

Generate a GEM XML file.

Parameters:
fp Pointer to opened file

void generate_MAP (  FILE *  fp  ) 
 

Generate a map XML file.

Parameters:
fp Pointer to opened file

void generate_TEM (  FILE *  fp  ) 
 

Generate a TEM XML file.

Parameters:
fp Pointer to opened file

void generate_TKR (  FILE *  fp  ) 
 

Generate a TKR XML file.

Parameters:
fp Pointer to opened file

int main (  int  argc,
char **  argv
) 
 

Generate all the XML files used by the QCFG tests.

Parameters:
argc Number of command line arguments
argv List of command line arguments
Returns:
0 on success

Variable Documentation

const Simple_register aem[N_AEM_REGISTER] [static]
 

Initial value:

 {
  {0xdeafabba, 4, 0x00000000, 0xfff0ff00, "trgseq" },
  {0x00000acd, 0, 0x00530000, 0x00000000, "aem_configuration"} 
}

const CCC_register ccc[N_CABLE] [static]
 

Initial value:

 {
  { 1, { {0x11111111, 1, 0, 0, "layer_mask_0"},
         {0x12121212, 2, 0, 0, "layer_mask_1"},
         {0x1f1f1f1f, 0, 0, 0, "ccc_configuration"},
         {0x16161616, 6, 0, 0, "ccc_trg_align"}    } },
  { 2, { {0x21212121, 1, 0, 0, "layer_mask_0"},
         {0x22222222, 2, 0, 0, "layer_mask_1"},
         {0x2f2f2f2f, 0, 0, 0, "ccc_configuration"},
         {0x26262626, 6, 0, 0, "ccc_trg_align"}    } }
}

const Simple_register dft_ccc[N_CCC_REGISTER] [static]
 

Initial value:

 {
  {0x01010101, 1, 0, 0, "layer_mask_0"},
  {0x02020202, 2, 0, 0, "layer_mask_1"},
  {0x0f0f0f0f, 0, 0, 0, "ccc_configuration"},
  {0x06060606, 6, 0, 0, "ccc_trg_alignment"}
}

const Simple_register dft_cfe[N_CFE_REGISTER] [static]
 

Initial value:

 {
  {0x01010101, 0, 0, 0, "config_0"},
  {0x02020202, 1, 0, 0, "config_1"},
  {0x0f0f0f0f, 2, 0, 0, "fle_dac"},
  {0x06060606, 3, 0, 0, "fhe_dac"},
  {0x05050505, 4, 0, 0, "log_acpt"},
  {0x0f0f0f0f, 5, 0, 0, "rng_uld_dac"},
  {0x06060606, 6, 0, 0, "ref_dac"}
}

const Simple_register dft_crc[N_CRC_REGISTER] [static]
 

Initial value:

 {
  {0x01010101, 3, 0, 0, "delay_1"},
  {0x02020202, 4, 0, 0, "delay_2"},
  {0x0f0f0f0f, 5, 0, 0, "delay_3"},
  {0x06060606, 6, 0, 0, "crc_dac"},
  {0x07070707, 7, 0, 0, "config"},
}

const Simple_register dft_tcc[N_TCC_REGISTER] [static]
 

Initial value:

 {
  {0x01010101, 0, 0, 0, "tcc_configuration"},
  {0x02020202, 1, 0, 0, "input_mask"},
  {0x0f0f0f0f, 5, 0, 0, "tcc_trg_align"}
}

const Simple_register dft_tem[N_TEM_REGISTER] [static]
 

Initial value:

 {
  {0x1f1f1f1f, 1, 0, 0xffffe000, "data_masks"},
  {0x5f5f5f5f, 5, 0, 0xfff0ff00, "cal_trgseq"},
  {0x4f4f4f4f, 4, 0, 0xfff0ff00, "tkr_trgseq"}
}

const Simple_register dft_tic[N_TIC_REGISTER] [static]
 

Initial value:

 {
  {0x2f2f2f2f, 2, 0, 0xffff0000, "cal_in_mask"    },
  {0x5f5f5f5f, 5, 0, 0xfffc0000, "tkr_layer_enable_0"},
  {0x6f6f6f6f, 6, 0, 0xfffc0000, "tkr_layer_enable_1"},
  {0x7f7f7f7f, 7, 0, 0xffff0000, "tkr_out_mask"      }
}

const TAM_engine engine[N_TAM_ENGINE] [static]
 

Initial value:

 {
  { 0x00, 1, 1, 1, 1, 1, 0, 0xf},
  { 0x11, 1, 1, 1, 1, 0, 1, 0xe},
  { 0x22, 1, 1, 1, 0, 0, 2, 0xd},
  { 0x33, 1, 1, 0, 0, 0, 3, 0xc},
  { 0x44, 1, 0, 0, 0, 0, 4, 0xb},
  { 0x55, 0, 0, 0, 0, 0, 5, 0xa},
  { 0x66, 0, 0, 0, 0, 1, 6, 0x9},
  { 0x77, 0, 0, 0, 1, 1, 7, 0x8},
  { 0x88, 0, 0, 1, 1, 1, 0, 0x7},
  { 0x99, 0, 1, 1, 1, 1, 1, 0x6},
  { 0xaa, 1, 0, 1, 0, 1, 2, 0x5},
  { 0xbb, 0, 1, 0, 1, 0, 3, 0x4},
  { 0xcc, 1, 1, 0, 1, 1, 4, 0x3},
  { 0xdd, 1, 0, 0, 0, 1, 5, 0x2},
  { 0xee, 0, 1, 1, 1, 0, 6, 0x1},
  { 0xff, 0, 0, 1, 0, 0, 7, 0x0}
}

const SCH_register sch[N_SCH_REGISTER] [static]
 

Initial value:

 {
  {"conditions_00_07", 0xffffffff},
  {"conditions_08_0F", 0x0fffffff},
  {"conditions_10_17", 0x00ffffff},
  {"conditions_18_1F", 0x000fffff},
  {"conditions_20_27", 0x0000ffff},
  {"conditions_28_2F", 0x00000fff},
  {"conditions_30_37", 0x000000ff},
  {"conditions_38_3F", 0x0000000f},
  {"conditions_40_47", 0x00000000},
  {"conditions_48_4F", 0xf0000000},
  {"conditions_50_57", 0xff000000},
  {"conditions_58_5F", 0xfff00000},
  {"conditions_60_67", 0xffff0000},
  {"conditions_68_6F", 0xfffff000},
  {"conditions_70_77", 0xffffff00},
  {"conditions_78_7F", 0xfffffff0}
}

const TEM_register tem[N_TWR] [static]
 

Initial value:

 {
  { 5, { {0x51515151, 1, 0, 0xffffe000, "data_masks"},
         {0x55555555, 5, 0, 0xfff0ff00, "cal_trgseq"},
         {0x54545454, 4, 0, 0xfff0ff00, "tkr_trgseq"} } },
  { 7, { {0x61616161, 1, 0, 0xffffe000, "data_masks"},
         {0x65656565, 5, 0, 0xfff0ff00, "cal_trgseq"},
         {0x64646464, 4, 0, 0xfff0ff00, "tkr_trgseq"} } }
}

const Simple_register tic[N_TWR][N_TIC_REGISTER] [static]
 

Initial value:

 {
  { {0x52525252, 2, 0, 0xffff0000, "cal_in_mask"    },
    {0x55555555, 5, 0, 0xfffc0000, "tkr_layer_enable_0"},
    {0x56565656, 6, 0, 0xfffc0000, "tkr_layer_enable_1"},
    {0x57575757, 7, 0, 0xffff0000, "tkr_out_mask"      } },
  { {0x62626262, 2, 0, 0xffff0000, "cal_in_mask"    },
    {0x65656565, 5, 0, 0xfffc0000, "tkr_layer_enable_0"},
    {0x66666666, 6, 0, 0xfffc0000, "tkr_layer_enable_1"},
    {0x67676767, 7, 0, 0xffff0000, "tkr_out_mask"      } },
}

const TIE_register tie[N_TIE_REGISTER] [static]
 

Initial value:

 {
  {"towers_0_3    ", 0x0000000f},
  {"towers_4_7    ", 0x000000f0},
  {"towers_8_b    ", 0x00000f00},
  {"towers_c_f    ", 0x000000ff},
  {"acd_cno       ", 0x00000ff0},
  {"tiles_000_013 ", 0x0003ffff},
  {"tiles_014_032 ", 0x0000ffff},
  {"tiles_033_NA3 ", 0x00030fff},
  {"tiles_100_113 ", 0x0003f0ff},
  {"tiles_114_NA5 ", 0x0003ff0f},
  {"tiles_200_213 ", 0x0003fff0},
  {"tiles_214_NA7 ", 0x0000000f},
  {"tiles_300_313 ", 0x000000ff},
  {"tiles_314_NA9 ", 0x00000fff},
  {"tiles_400_413 ", 0x0000ffff},
  {"tiles_414_NA1 ", 0x0003ffff},
  {"tiles_500_NA10", 0x0003c3c3},
  {"tower_busy    ", 0x00005a5a}
}

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