MON_perf_regs.h File Reference
RAD750 performance monitor register definitions.
More...
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Defines |
#define | MON_PERF_REG_MASK(tag, field) |
| Create an in-place bit mask from size and right-offset values.
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#define | MON_PERF_REG_VALUE(value, tag, field) (((value) << (tag ## _V_ ## field)) & MON_PERF_REG_MASK (tag, field)) |
| Shift and mask a value into a register field.
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Typedefs |
typedef enum _MON_MMCR0_S | MON_MMCR0_S |
| Typedef for _MON_MMCR0_S.
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typedef enum _MON_MMCR0_V | MON_MMCR0_V |
| Typedef for _MON_MMCR0_V.
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typedef enum _MON_MMCR1_S | MON_MMCR1_S |
| Typedef for _MON_MMCR1_S.
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typedef enum _MON_MMCR1_V | MON_MMCR1_V |
| Typedef for _MON_MMCR1_V.
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Enumerations |
enum | _MON_MMCR0_S {
MON_MMCR0_S_DIS = 1,
MON_MMCR0_S_DP = 1,
MON_MMCR0_S_DU = 1,
MON_MMCR0_S_DMS = 1,
MON_MMCR0_S_DMR = 1,
MON_MMCR0_S_ENINT = 1,
MON_MMCR0_S_DISCOUNT = 1,
MON_MMCR0_S_RTCSELECT = 2,
MON_MMCR0_S_INTONBITTRANS = 1,
MON_MMCR0_S_THRESHOLD = 6,
MON_MMCR0_S_PMC1INTCONTROL = 1,
MON_MMCR0_S_PMCINTCONTROL = 1,
MON_MMCR0_S_PMCTRIGGER = 1,
MON_MMCR0_S_PMC1SELECT = 7,
MON_MMCR0_S_PMC2SELECT = 6
} |
| Size. in bits, of each MMCR0 register field. More...
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enum | _MON_MMCR0_V {
MON_MMCR0_V_DIS = 31,
MON_MMCR0_V_DP = 30,
MON_MMCR0_V_DU = 29,
MON_MMCR0_V_DMS = 28,
MON_MMCR0_V_DMR = 27,
MON_MMCR0_V_ENINT = 26,
MON_MMCR0_V_DISCOUNT = 25,
MON_MMCR0_V_RTCSELECT = 23,
MON_MMCR0_V_INTONBITTRANS = 22,
MON_MMCR0_V_THRESHOLD = 16,
MON_MMCR0_V_PMC1INTCONTROL = 15,
MON_MMCR0_V_PMCINTCONTROL = 14,
MON_MMCR0_V_PMCTRIGGER = 13,
MON_MMCR0_V_PMC1SELECT = 6,
MON_MMCR0_V_PMC2SELECT = 0
} |
| Right-justified offset, in bits, of each MMCR0 register field. More...
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enum | _MON_MMCR1_S {
MON_MMCR1_S_PMC3SELECT = 5,
MON_MMCR1_S_PMC4SELECT = 5
} |
| Size. in bits, of each MMCR1 register field. More...
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enum | _MON_MMCR1_V {
MON_MMCR1_V_PMC3SELECT = 27,
MON_MMCR1_V_PMC4SELECT = 22
} |
| Right-justified offset, in bits, of each MMCR1 register field. More...
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Detailed Description
RAD750 performance monitor register definitions.
** CVS $Id: MON_perf_regs.h,v 1.1.1.1 2005/03/10 22:16:39 dmay Exp $
**
Defines constants and macros that describe the registers associated with the RAD750 performance monitor facility.
Define Documentation
#define MON_PERF_REG_MASK |
( |
tag, |
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field |
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) |
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Value:
((((unsigned int)0xffffffff) >> (32-(tag ## _S_ ## field))) \
<< (tag ## _V_ ## field))
Create an in-place bit mask from size and right-offset values.
Enumeration Type Documentation
Size. in bits, of each MMCR0 register field.
- Enumerator:
-
MON_MMCR0_S_DIS |
'Unconditional count disable' field size, in bits |
MON_MMCR0_S_DP |
'Supervisor mode count disable' field size, in bits. |
MON_MMCR0_S_DU |
'User mode count disable' field size, in bits. |
MON_MMCR0_S_DMS |
'Set-MSR[PM] count disable' field size, in bits. |
MON_MMCR0_S_DMR |
'Clear-MSR[PM] count disable' field size, in bits. |
MON_MMCR0_S_ENINT |
'Performance monitor interrupt enable' field size, in bits. |
MON_MMCR0_S_DISCOUNT |
'Interrupt count disable' field size, in bits. |
MON_MMCR0_S_RTCSELECT |
'Time base bit selection' field size, in bits. |
MON_MMCR0_S_INTONBITTRANS |
'Bit transition interrupt enable' field size, in bits. |
MON_MMCR0_S_THRESHOLD |
'Threshold' field size, in bits. |
MON_MMCR0_S_PMC1INTCONTROL |
'PMC1 overflow interrupt enable' field size, in bits. |
MON_MMCR0_S_PMCINTCONTROL |
'PMC2-PMC4 overflow interrupt enable' field size, in bits. |
MON_MMCR0_S_PMCTRIGGER |
'PMC2-PMC4 trigger enable' field size, in bits. |
MON_MMCR0_S_PMC1SELECT |
'PMC1 event selection' field size, in bits. |
MON_MMCR0_S_PMC2SELECT |
'PMC2 event selection' field size, in bits. |
Right-justified offset, in bits, of each MMCR0 register field.
- Enumerator:
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MON_MMCR0_V_DIS |
'Unconditional count disable' field right-offset, in bits |
MON_MMCR0_V_DP |
'Supervisor mode count disable' field right-offset, in bits. |
MON_MMCR0_V_DU |
'User mode count disable' field right-offset, in bits. |
MON_MMCR0_V_DMS |
'Set-MSR[PM] count disable' field right-offset, in bits. |
MON_MMCR0_V_DMR |
'Clear-MSR[PM] count disable' field right-offset, in bits. |
MON_MMCR0_V_ENINT |
'Performance monitor interrupt enable' field right-offset, in bits. |
MON_MMCR0_V_DISCOUNT |
'Interrupt count disable' field right-offset, in bits. |
MON_MMCR0_V_RTCSELECT |
'Time base bit selection' field right-offset, in bits. |
MON_MMCR0_V_INTONBITTRANS |
'Bit transition interrupt enable' field right-offset, in bits. |
MON_MMCR0_V_THRESHOLD |
'Threshold' field right-offset, in bits. |
MON_MMCR0_V_PMC1INTCONTROL |
'PMC1 overflow interrupt enable' field right-offset, in bits. |
MON_MMCR0_V_PMCINTCONTROL |
'PMC2-PMC4 overflow interrupt enable' field right-offset, in bits. |
MON_MMCR0_V_PMCTRIGGER |
'PMC2-PMC4 trigger enable' field right-offset, in bits. |
MON_MMCR0_V_PMC1SELECT |
'PMC1 event selection' field right-offset, in bits. |
MON_MMCR0_V_PMC2SELECT |
'PMC2 event selection' field right-offset, in bits. |
Size. in bits, of each MMCR1 register field.
- Enumerator:
-
MON_MMCR1_S_PMC3SELECT |
'PMC3 event selection' field size, in bits. |
MON_MMCR1_S_PMC4SELECT |
'PMC4 event selection' field size, in bits. |
Right-justified offset, in bits, of each MMCR1 register field.
- Enumerator:
-
MON_MMCR1_V_PMC3SELECT |
'PMC3 event selection' field right-offset, in bits. |
MON_MMCR1_V_PMC4SELECT |
'PMC4 event selection' field right-offset, in bits. |