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ppciInt.h File Reference

Function prototypes for primary and miscellaneous PowerPCI interrupt routing. More...

#include "vxWorks.h"

Include dependency graph for ppciInt.h:

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Primary PowerPCI interrupts

typedef enum ppciIntLvl ppciIntLvl_t
enum  ppciIntLvl {
  PCI_INT_LVL = 31,
  P60X_INT_LVL = 30,
  MEM_HI_INT_LVL = 26,
  MEM_LOW_INT_LVL = 25,
  UART_INT_LVL = 24,
  EMC_INT_LVL = 23,
  MISC_INT_LVL = 22,
  CAT_INT_LVL = 21,
  PID_INT_LVL = 15,
  SIG_INT_LVL = 14
}
STATUS ppciIntEnable (ppciIntLvl_t intLvl)
 Enable a PowerPCI interrupt level.
STATUS ppciIntDisable (ppciIntLvl_t intLvl)
 Disable a PowerPCI interrupt level.
STATUS ppciIntConnect (ppciIntLvl_t intLvl, VOIDFUNCPTR isr, int parm)
 Connect ISR to PowerPCI interrupt level.
void ppciIntInit (void)
void ppciIntInit2 (void)

Miscellaneous PowerPCI interrupts

typedef enum miscIntLvl miscIntLvl_t
enum  miscIntLvl {
  PTIM1_INT_LVL = 31,
  PTIM2_INT_LVL = 30,
  PTIM3_INT_LVL = 29,
  ADDR_PH_PE_INT_LVL = 28,
  WRT_DATA_PE_INT_LVL = 27,
  WRT_ACC_PE_INT_LVL = 26
}
STATUS miscIntEnable (miscIntLvl_t intLvl)
 Enable a PowerPCI MISC interrupt level.
STATUS miscIntDisable (miscIntLvl_t intLvl)
 Disable a PowerPCI MISC interrupt level.
STATUS miscIntConnect (miscIntLvl_t intLvl, VOIDFUNCPTR isr, int parm)
 Connect ISR to PowerPCI MISC interrupt level.

PCI error PowerPCI interrupts

typedef enum pciIntLvl pciIntLvl_t
enum  pciIntLvl {
  PCI_ERR_TARGET_READY_PAR = 0,
  PCI_ERR_TARGET_DATA_PAR = 1,
  PCI_ERR_TARGET_PERR = 2,
  PCI_ERR_MEM_SPACE_OVERLAP = 3,
  PCI_ERR_INIT_READY_PAR = 4,
  PCI_ERR_INIT_DATA_PAR = 5,
  PCI_ERR_INIT_PERR = 6,
  PCI_ERR_ARBITER_LAT_TIMEOUT = 8,
  PCI_ERR_DATA_PHASE_TIMEOUT = 9,
  PCI_ERR_ARBITER_TIMEOUT = 10,
  PCI_ERR_ADDRESS_PAR = 11,
  PCI_ERR_SERR_RCV = 12,
  PCI_ERR_PROTOCOL = 13,
  PCI_ERR_RESET = 14,
  PCI_ERR_INTERNAL_REG = 15,
  PCI_ERR_OCB_ADDRESS_PAR = 16,
  PCI_ERR_OCB_ADDRESS_INV = 17,
  PCI_ERR_OCB_ACCESS_INV = 18,
  PCI_ERR_OCB_SLAVE_DATA_PAR = 19,
  PCI_ERR_OCB_SLAVE_BE_PAR = 20,
  PCI_ERR_OCB_WRITE_BUF_PAR = 21,
  PCI_ERR_OCB_MASTER_DATA_PAR = 22,
  PCI_ERR_OCB_MASTER_READ = 23,
  PCI_ERR_MASTER_DATA_PAR = 24,
  PCI_ERR_TARGET_ABORT_SIG = 27,
  PCI_ERR_TARGET_ABORT_RCV = 28,
  PCI_ERR_MASTER_ABORT_RECV = 29,
  PCI_ERR_SERR_SIG = 30,
  PCI_ERR_PAR_ERR_RCV = 31
}
STATUS pciErrIntEnable (pciIntLvl_t intLvl)
 Enable a PowerPCI PCI error interrupt level.
STATUS pciErrIntDisable (pciIntLvl_t intLvl)
 Disable a PowerPCI PCI error interrupt level.
STATUS pciErrIntConnect (pciIntLvl_t intLvl, VOIDFUNCPTR isr, int parm)
 Connect ISR to PowerPCI PCI error interrupt level.

P60X error PowerPCI interrupts

typedef enum p60xIntLvl p60xIntLvl_t
enum  p60xIntLvl {
  P60X_ERR_MEM_CTRL_IF = 0,
  P60X_ERR_ADDR_RANGE = 1,
  P60X_ERR_OCB_IF = 2
}
STATUS p60xErrIntEnable (p60xIntLvl_t intLvl)
 Enable a PowerPCI PCI error interrupt level.
STATUS p60xErrIntDisable (p60xIntLvl_t intLvl)
 Disable a PowerPCI PCI error interrupt level.
STATUS p60xErrIntConnect (p60xIntLvl_t intLvl, VOIDFUNCPTR isr, int parm)
 Connect ISR to PowerPCI PCI error interrupt level.

Detailed Description

Function prototypes for primary and miscellaneous PowerPCI interrupt routing.

-------------------------------------------------------------------------

Description:

This file defines function prototypes for primary and miscellaneous PowerPCI interrupt routing. Functions for routing PID interrupts are defined in ppciPid.h. Functions for routing multiprocessor signal interrupts are defined in ppciMp.h. Note that ppciPtim.h provides timer interrupt routing functions that wrap the miscInt*() functions defined here. Also note that typical RAD750 BSPs define the standard VxWorks interrupt routines (intEnable(), intDisable() and intConnect()) for routing PCI interrupt signals wired into PowerPCI PIDs.

See ppciInt.c for detailed descriptions of the function prototypes defined in this header file.

Restrictions:

Change History:

Date Pgm Description -------- --- ------------------------------------------------------- 04/21/00 MJF Initial Release 01/03/01 DS BSP integration.

--------------------------------------------------------------------------

Typedef Documentation

miscIntLvl_t
 

The typedef for miscIntLvl.

p60xIntLvl_t
 

The typedef for p60xIntLvl.

pciIntLvl_t
 

The typedef for pciIntLvl.

ppciIntLvl_t
 

The typedef for ppciIntLvl.

Enumeration Type Documentation

enum miscIntLvl
 

The PPCI miscellaneous interrupt level values.

Enumerator:
PTIM1_INT_LVL  PPCI miscellaneous interrupt level
PTIM2_INT_LVL  PPCI miscellaneous interrupt level
PTIM3_INT_LVL  PPCI miscellaneous interrupt level
ADDR_PH_PE_INT_LVL  PPCI miscellaneous interrupt level
WRT_DATA_PE_INT_LVL  PPCI miscellaneous interrupt level
WRT_ACC_PE_INT_LVL  PPCI miscellaneous interrupt level

enum p60xIntLvl
 

The P60X interface interrupt levels.

Enumerator:
P60X_ERR_MEM_CTRL_IF  P60X interface interrupt level.
P60X_ERR_ADDR_RANGE  P60X interface interrupt level.
P60X_ERR_OCB_IF  P60X interface interrupt level.

enum pciIntLvl
 

The PCI error interrupt level values.

Enumerator:
PCI_ERR_TARGET_READY_PAR  PCI error interrupt level.
PCI_ERR_TARGET_DATA_PAR  PCI error interrupt level.
PCI_ERR_TARGET_PERR  PCI error interrupt level.
PCI_ERR_MEM_SPACE_OVERLAP  PCI error interrupt level.
PCI_ERR_INIT_READY_PAR  PCI error interrupt level.
PCI_ERR_INIT_DATA_PAR  PCI error interrupt level.
PCI_ERR_INIT_PERR  PCI error interrupt level.
PCI_ERR_ARBITER_LAT_TIMEOUT  PCI error interrupt level.
PCI_ERR_DATA_PHASE_TIMEOUT  PCI error interrupt level.
PCI_ERR_ARBITER_TIMEOUT  PCI error interrupt level.
PCI_ERR_ADDRESS_PAR  PCI error interrupt level.
PCI_ERR_SERR_RCV  PCI error interrupt level.
PCI_ERR_PROTOCOL  PCI error interrupt level.
PCI_ERR_RESET  PCI error interrupt level.
PCI_ERR_INTERNAL_REG  PCI error interrupt level.
PCI_ERR_OCB_ADDRESS_PAR  PCI error interrupt level.
PCI_ERR_OCB_ADDRESS_INV  PCI error interrupt level.
PCI_ERR_OCB_ACCESS_INV  PCI error interrupt level.
PCI_ERR_OCB_SLAVE_DATA_PAR  PCI error interrupt level.
PCI_ERR_OCB_SLAVE_BE_PAR  PCI error interrupt level.
PCI_ERR_OCB_WRITE_BUF_PAR  PCI error interrupt level.
PCI_ERR_OCB_MASTER_DATA_PAR  PCI error interrupt level.
PCI_ERR_OCB_MASTER_READ  PCI error interrupt level.
PCI_ERR_MASTER_DATA_PAR  PCI error interrupt level.
PCI_ERR_TARGET_ABORT_SIG  PCI error interrupt level.
PCI_ERR_TARGET_ABORT_RCV  PCI error interrupt level.
PCI_ERR_MASTER_ABORT_RECV  PCI error interrupt level.
PCI_ERR_SERR_SIG  PCI error interrupt level.
PCI_ERR_PAR_ERR_RCV  PCI error interrupt level.

enum ppciIntLvl
 

PPCI master interrupt level values.

Enumerator:
PCI_INT_LVL  PPCI master interrupt level.
P60X_INT_LVL  PPCI master interrupt level.
MEM_HI_INT_LVL  PPCI master interrupt level.
MEM_LOW_INT_LVL  PPCI master interrupt level.
UART_INT_LVL  PPCI master interrupt level.
EMC_INT_LVL  PPCI master interrupt level.
MISC_INT_LVL  PPCI master interrupt level.
CAT_INT_LVL  PPCI master interrupt level.
PID_INT_LVL  PPCI master interrupt level.
SIG_INT_LVL  PPCI master interrupt level.

Function Documentation

STATUS miscIntConnect (  miscIntLvl_t  intLvl,
VOIDFUNCPTR  isr,
int  parm
) 
 

Connect ISR to PowerPCI MISC interrupt level.

Connect ISR to PowerPCI MISC interrupt level

This routine connects an interrupt service routine (ISR) to PowerPCI bridge MISC interrupt level. Note that the MISC interrupts include the programmable timer interrupts (PTIM). MISC interrupts are enabled separate from this routine (by miscIntEnable()). The interrupt level being connected should not be enable when this routine is called. The specified ISR will get control with interrupts disabled.

Parameters:
intLvl - The PPCI MISC interrupt level.
isr - Pointer to the ISR.
parm - A user-defined parameter to pass to the ISR when the interrupt occurs.
Returns:
OK or ERROR

STATUS miscIntDisable (  miscIntLvl_t  intLvl  ) 
 

Disable a PowerPCI MISC interrupt level.

Disable a PowerPCI MISC interrupt level

This routine disables the specified MISC interrupt level of the PowerPCI bridge. Note that the MISC interrupts include the programmable timer interrupts (PTIM).

Parameters:
intLvl - The PPCI MISC interrupt level to disable.
Returns:
OK or ERROR

STATUS miscIntEnable (  miscIntLvl_t  intLvl  ) 
 

Enable a PowerPCI MISC interrupt level.

Enable a PowerPCI MISC interrupt level

This routine enables the specified MISC interrupt level of the PowerPCI bridge. The Note that the MISC interrupts include the programmable timer interrupts (PTIM).

Parameters:
intLvl - The PPCI MISC interrupt level to enable.
Returns:
OK or ERROR.

STATUS p60xErrIntDisable (  p60xIntLvl_t  intLvl  ) 
 

Disable a PowerPCI PCI error interrupt level.

Enable a PowerPCI P60X error interrupt level

This routine disables the specified P60X error interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI P60X error interrupt level to disable.
Returns:
OK or ERROR.

STATUS p60xErrIntEnable (  p60xIntLvl_t  intLvl  ) 
 

Enable a PowerPCI PCI error interrupt level.

Enable a PowerPCI P60X error interrupt level

This routine enables the specified P60X error interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI P60X error interrupt level to enable.
Returns:
OK or ERROR.

STATUS pciErrIntConnect (  pciIntLvl_t  intLvl,
VOIDFUNCPTR  isr,
int  parm
) 
 

Connect ISR to PowerPCI PCI error interrupt level.

Connect ISR to PowerPCI PCI error interrupt level

This routine connects an interrupt service routine (ISR) to PowerPCI bridge PCI error interrupt level. PCI error interrupts are enabled separate from this routine (by pciErrIntEnable()). The interrupt level being connected should not be enabled when this routine is called. The specified ISR will get control with interrupts disabled.

Parameters:
intLvl - The PPCI PCI error interrupt level.
isr - Pointer to the ISR.
parm - A user-defined parameter to pass to the ISR when the interrupt occurs.
Returns:
OK or ERROR

STATUS pciErrIntDisable (  pciIntLvl_t  intLvl  ) 
 

Disable a PowerPCI PCI error interrupt level.

Disable a PowerPCI PCI error interrupt level

This routine disables the specified PCI error interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI PCI error interrupt level to disable.
Returns:
OK or ERROR

STATUS pciErrIntEnable (  pciIntLvl_t  intLvl  ) 
 

Enable a PowerPCI PCI error interrupt level.

Enable a PowerPCI PCI error interrupt level

This routine enables the specified PCI error interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI PCI error interrupt level to enable.
Returns:
OK or ERROR.

STATUS ppciIntConnect (  ppciIntLvl_t  intLvl,
VOIDFUNCPTR  isr,
int  parm
) 
 

Connect ISR to PowerPCI interrupt level.

Connect ISR to PowerPCI interrupt level

This routine connects an interrupt service routine (ISR) to PowerPCI bridge interrupt level. PPCI interrupts are enabled separate from this routine (by ppciIntEnable). The interrupt level being connected should not be enable when this routine is called. The specified ISR will get control with interrupts disabled.

Parameters:
intLvl - The PPCI interrupt level.
isr - Pointer to the ISR.
parm - A user-defined parameter to pass to the ISR when the interrupt occurs.
Returns:
OK or ERROR

STATUS ppciIntDisable (  ppciIntLvl_t  intLvl  ) 
 

Disable a PowerPCI interrupt level.

Disable a PowerPCI interrupt level

This routine disables the specified interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI interrupt level to disable.
Returns:
OK or ERROR.

STATUS ppciIntEnable (  ppciIntLvl_t  intLvl  ) 
 

Enable a PowerPCI interrupt level.

Enable a PowerPCI interrupt level

This routine enables the specified interrupt level of the PowerPCI bridge.

Parameters:
intLvl - The PPCI interrupt level to enable.
Returns:
OK or ERROR.

void ppciIntInit (  void   ) 
 

Interrupt initialization routine, first part.

This init routine is called by ppciInit (from sysHwInit) during system boot. Interrupt routing resources are initialized.

void ppciIntInit2 (  void   ) 
 

Interrupt initialization routine, second part

This init routine is called by ppciInit2 (from sysHwInit2) during system boot. Default handlers are installed for the PPCI error interrupts.

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