LAT System Initialization

A Beginning

Curt Brune

Stanford Linear Accelerator Center (SLAC)
GLAST Flight Software

Revision History
Revision 0.1	July 16, 2002

This document provides an overview of the LAT System Initialization (LSI).

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Table of Contents

Introduction

1. Definitions

2. Assumptions

2.1. Hardware Assumptions

1. cPCI Crate Initialization

1.1. Configuring the Director SBC

1.2. Configuring the PCI Bus

1.2.1. Base Address Registers (BAR)
1.2.2. Interrupt Pin
1.2.3. Command and Status Registers in PCI Configuration Space

1.3. Configuring and enabling the SIB

1.4. Configuring the Actor SBCs

1.5. Configuring the LCB

1.5.1. Configuring the Event Circular Buffers
1.5.2. Enabling the LCB

1.6. Memory Maps

1.6.1. SIB Memory Maps
1.6.2. LCB and SBC Memory Maps

1.7. LSI Timing Diagram

1.7.1. PCI Crate Initialization Timing Diagram
1.7.2. Single Actor SBC Reboot Timing Diagram

Background Documentation

List of Tables
1-1. SBC DMA spaces

List of Figures
1. Layout of the PCI bus in a single cPCI crate.
1-1. Example LCB to PCI I/O Space Memory Map.
1-2. Example LCB to PCI Memory Space Memory Map.
1-3. Example NRL SBC to PCI I/O Space Memory Map.
1-4. Example NRL SBC to PCI Memory Space Memory Map.
1-5. Example PCI I/O Space Memory Map for single PCI crate.
1-6. Example PCI Memory Space Memory Map for single PCI crate.
1-7. Timing of PCI module configuration during PCI crate initialization
1-8. Timing of Actor SBC rebooting

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		Introduction